ERC-50 10K Search Results

Contextual Info: CDCUN1208LP www.ti.com SCAS928A – MAY 2012 – REVISED JANUARY 2013 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES 1 • • • • • Support PCIE gen1, gen2, gen3 Configuration Options via pins or SPI/I2C :

Contextual Info: CDCUN1208LP www.ti.com SCAS928 – MAY 2012 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES • 1 • • • • 2 Configuration Options via pins or SPI/I C : – Input Type (HCSL, LVDS, LVCMOS)

Contextual Info: SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP

Contextual Info: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

173KB

Contextual Info: SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • • • • Member of Texas Instruments' Widebus Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in

Contextual Info: SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 FEATURES • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

Dielectric Resonator Oscillator DRO

Abstract: CHV2241 DRD036EC016 Substrate alumina
Contextual Info: CHV2241 K-band Oscillator with integrated Q-band Harmonic Mixer GaAs Monolithic Microwave IC Description The CHV2241 is a monolithic multifunction proposed for frequency generation and transposition. It integrates a K-band oscillator, a Q-band harmonic mixer and buffer amplifiers.

Signal path designer

Contextual Info: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

Signal Path Designer

Contextual Info: SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 FEATURES • • • • • • RGY PACKAGE TOP VIEW D, DGV, OR PW PACKAGE

Signal path designer

Abstract: cpci backplane schematic
Contextual Info: SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D D D D, DGV, OR PW PACKAGE TOP VIEW TI-OPC Circuitry Limits Ringing on

Contextual Info: SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 D D D D D D D D D D D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family

Signal Path Designer

Contextual Info: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

IBIS Models

Abstract: TTL 74 sl 90 Signal Path designer
Contextual Info: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Signal Path Designer

Contextual Info: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Signal path designer

Contextual Info: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

Contextual Info: SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 D D D D D D D D D D D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family

Signal Path designer

Contextual Info: SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Signal Path designer

Contextual Info: SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Signal Path Designer

Contextual Info: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

TTL 74 sl 90

Abstract: Signal Path Designer
Contextual Info: SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

TTL 74 sl 90

Abstract: Signal Path Designer
Contextual Info: SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

smd transistor 712

Contextual Info: ELECTRONICS TCXO OSCILLATORS -30 to +75ºC ER Models,SMD TCXO 11.4 x 9.6 mm 2.5 PPM, 3.0 or 5.0V SURFACE MOUNT ER-A, ER-B, ER-C ER-D 12.0 MHz to 19.68 MHz FIXED FREQUENCY These surface mount oscillators are available in eight standard frequencies. Other frequencies on special order

Signal Path Designer

Abstract: 5V 5 point RELAY
Contextual Info: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information