ERASABLE PROGRAMMABLE LOGIC DEVICE 610 Search Results

Contextual Info: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

27C400 eprom

Abstract: 27C400 tms27c400 K1631 27PC40
Contextual Info: TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC400 4 194 304-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS400A-OCTOBER 1992-REVISED JANUARY 1993 Word-Wide 256K x 16 or Byte-Wide (512K x 8) Configurable 4-Megablt Mask ROM Compatible - 40-Lead CERDIP Package

TTL 7400

Abstract: CY7C342 7400 datasheet ttl gate 7400 series CMOS Logic ICs 7400 series logic ICs 7400 TTL datasheet CY7C342B 7400series ttl cmos logic 7400 series
Contextual Info: This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. 1CY 7C34 2 fax id: 6103 CY7C342 128-Macrocell MAX EPLDs Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins

texas ic 6116

Contextual Info: TMS27C512 524.288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC512 524,288 BIT PROGRAMMABLE READ-ONLY MEMORY N O VEM BER 1985 - This Data Sheet is Applicable to AH TMS27C512s and TMS27PC512s Symbolized w ith Code "A " as Described on Page 12. J AND N PACKAGE

tms27pc256

Abstract: cm2 5612 TMS27C256JL S27C256 FML 612
Contextual Info: TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY REVA SMLS256E - SEPTEMBER 1964 This Data Sheet is Applicable to All TMS27C256S and TMS27PC256s Symbolized with Code “B" as Described on Page 7-25.

pc 2561

Abstract: S27C256 27PC256NL
Contextual Info: TMS27C256 262.144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262,144-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEMBER 1 9 8 4 -REVISED MARCH 1988 This Data Sheet is Applicable to A ll TMS27C256S a nd TMS27PC256s Sym bolized w ith Code " A " as Described on Page 12.

7400 series logic ICs

Abstract: CY7C341 CY7C341B
Contextual Info: fax id: 6105 1CY 7C34 1 This is an abbreviated data sheet. Contact a Cypress Representative for complete specifications. For new designs please refer to the CY7C341B. CY7C341 192-Macrocell MAX EPLD Features • • • • • • 92 macrocells in 12 LABs

tms jl 27C512

Abstract: TMS27C512JE SMJ27C
Contextual Info: TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PCS12 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY 0 D 7 7 S 1 ? fl 'N O VEM B ER 1985 - REVISED APRIL 1988 J AND N PACKAGE T - t/ 6 * / 3 mZ $ ‘ TOP VIEW T ~ y é '/ 3 '¿ f A 1 5 C 1 1J 2 8 □ v c c

27C256-16

Abstract: tms jl 27c256-12
Contextual Info: • fllk lT SS 0 0 7 7 2 0 3 â ■ TMS27C256 262,144BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC2S6 262,144 BIT PROGRAMMABLE READ-ONLY MEMORY TEXAS INSTR ASIC/MEMORY 25E D SEPTEMBER 1964—revised march 19sb This Data Sheet is Applicable to AH

2956

Abstract: 1065002 MN170
Contextual Info: TMS28F010A 1048576-BIT FUSH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM JS012-DECEM BER 1992-R E V IS E D NOVEMBER 1993 N PACKAGE O rganization. . . 128K x 8-Bit Flash Memory Pin Com patible W ith Existing 1-Megabit EPROMs V q c Tolerance ±10%

Contextual Info: COM’L: H-15/25 MIL: H-20 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 H Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 SI PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: a Advanced Micro Devices <7 PALCE16V8H-15/25 EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pin GAL devices ■ Electrically erasable CMOS technology provides reconfigurable logic and full

Contextual Info: AMDH COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic ?. *.? eoV . . s DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

12950G

Contextual Info: COM'L: H-15/25 FINAL PALCE610 Family AdvaM Tro EE CMOS High Performance Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

EP610

Abstract: PALCE610 CE610H
Contextual Info: FINAL COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

PALCE610H-25

Abstract: EP610 PALCE610 lattice 1996
Contextual Info: FINAL COM’L: H-15/25 Lattice/Vantis PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

EP610

Abstract: PALCE610 sr flipflop
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-15/25 Lattice Semiconductor PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

12950-012a

Contextual Info: Preliminary COM’L i PALCE61 OH-15/25 l Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

TI EP610

Contextual Info: PALCE610 Family AdVMi“ro EE CMOS High Performance Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins ■

Pal programming

Abstract: EP610 PALCE610 EP610 ORDERING EP610 "pin compatible"
Contextual Info: COM’L: H-15/25 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins