EQUIVALENT TRANSISTOR A1020 Y 7 B Search Results

Contextual Info: Array Architecture for ATG with 100% Fault Coverage Abstract This paper discusses array architecture, circuitry and methodology for the autom atic generation o f test vectors. T he architecture is im plem ented in a mask programm ed version of an antifuse based

A1010

Abstract: A1010B A1020 A1020B transistor A1010
Contextual Info: ACT 1 Series FPGAs • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

A1020B

Abstract: a1010b transistor a1020 A1010 A1020 transistor A1010
Contextual Info: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

Contextual Info: ACT 1 Series FPGAs Features • A security fuse may be programmed to disable all further programming and to protect the design from being copied or 5Vand 3.3V Fam iliesfully compatible with JEDEC reverse engineered. specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

A1010-PL

Abstract: Microsoft 007 ird
Contextual Info: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

Actel a1280

Abstract: VKS FPGA CQFP 172 actel 1020 A1020 smd TRANSISTOR 5962-9215601MXA 5962-9096503MTC equivalent transistor A1020 y 7 b Actel A1020 ACTEL A1010 actel 1020 datasheet
Contextual Info: Military Field Programmable Gate Arrays Features ACT 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Device Sizes from 1200 to 10,000 gates up to 25,000 PLD equivalent gates • Up to 4, Fast, Low-Skew Clock Networks

orcad

Contextual Info: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates

A1010APG84B

Abstract: A1280Acq
Contextual Info: ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • * U p to 2000 G ate A rray G ates 6000 PL D eq u iv alen t gates • R eplaces up to 53 T T L P ackages • R eplaces up to seventeen 20-P in PAL Packages •

RH1020

Abstract: A1020 A1280 CQ84 RH1280
Contextual Info: Radiation-Hardened Field Programmable Gate Arrays Features • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and

2001TL

Abstract: actel die run marking
Contextual Info: Æ lctel Radiation-Hardened Field Programmable Gate Arrays F e a tu re s • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and

Contextual Info: Æ ic te - m ! v 2 .0 Radiation-Hardened Field Programmable Gate Arrays Features Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Im m unity Guaranteed QML Qualified Devices

Contextual Info: — > 1 ! i Features Product Summary fcM Figure 1 • Partial View o f an ACT 1 Device A C T 1 D e v ic e S tru c tu re A partial view of an ACT 1 device Figure 1 depicts four logic modules and distributed horizontal and vertical Interconnect tracks. PLICE antifuses, located at intersections of the

Contextual Info: RadHard Field Programmable Gate Arrays Features P ro d u c t F am ily P rofile • Guaranteed Total Dose Radiation Capabilit Device • Low Single Event Upset Susceptibility RH1020 RH1280 Capacity • High Dose Rate Survivability 2 ,0 0 0 8 ,0 00 6 ,0 0 0

Actel a1280

Abstract: A1280 ACTEL burn-in VKS FPGA CQFP 106 A1020 RH1020 RH1280 RT1020 lockheed-martin CQFP 172 PIN
Contextual Info: v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and

h128 transistor

Abstract: transistors H128 NH FUSE LINDER BSC 25-05 quivalent book
Contextual Info: RadHard Field Programmable Gate Arrays F e a ftw s re s Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High D oseR ateS urvivability Latch-Up Im m unity Guaranteed QML Qualified Devices Commercial Devices A vailablefor Prototyping and

RT14100A

Abstract: rt1280 VKS FPGA CQFP 172 RT1280A CQFP 172 PIN 172-PIN A1280A VKS RT1460 VKS FPGA CQFP 106 A1020B
Contextual Info: v3.1 RadTolerant FPGAs Features General Characteristics • • • • • • Tested Total Ionizing Dose TID Survivability Level No Single Event Latch-Up Below a Minimum LET (Linear Energy Transfer) Threshold of 80 MeV-cm2/mg for All RT (RadTolerant) Devices

CQFP 256 PIN actel

Abstract: RT1280A A1280A VKS rt1280 A1020B ACTEL A1280A A1020 transistor A1280A-CQ172C RT1460 actel 172 cqfp
Contextual Info: v3.1 RadTolerant FPGAs Features General Characteristics • • • • • • Tested Total Ionizing Dose TID Survivability Level No Single Event Latch-Up Below a Minimum LET (Linear Energy Transfer) Threshold of 80 MeV-cm2/mg for All RT (RadTolerant) Devices

A1020 Y

Abstract: smd transistor E5 GHL 88
Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • System Performance to i( MHz over Military Temperature

Contextual Info: ACT 1 and A C T 2 Military Field P rogram m able G ate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL Packages • Design Library with over 250 Macros

5962-9096504MTA

Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family Device Sizes from 1200 to 10,000 gates up to 25,000 PLD

A1020A-CQ84B

Abstract: actel package mechanical drawing 5962-9096501MXX TA273 actel a1240 A1020APG84B smd transistor l7 A1020A-JQ84B DEC4X16A "alu 4 bit"
Contextual Info: ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 P L D / L C A ™ equivalent gates • Up to 8000 Gate A rray Gates (20,000 P L D /L C A ™ equivalent gates) • Replaces up to 53 T T L Packages

5962-9552102MYA

Abstract: 5962-9215601MYA 5962-9322101M 5962-9215602mxa A1020B-PG84B 5962-9552102mxa 152 LSK
Contextual Info: Military Field Programmable Gate Arrays Features ACT 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • Device Sizes from 1200 to 10,000 gates up to 25,000 PLD

A3200DX

Abstract: DIODE 044 1334 smd 5962-9215602MXA 5962-9552001MYC A1280XL A32100DX A32140DX 5962-9215602MYA A32300DX Resistor SMD 310
Contextual Info: HiRel Field Programmable Gate Arrays Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 30,000 gates • Highest Speed FPGA SRAM, up to 4 Kbits Configurable

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A1280A-PG176B 32200D smd transistor JJ
Contextual Info: = * 4 c t e ml HiRel FPGAs Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 20,000 gates • Highest Speed FPGA SRAM, up to 2.5 Kbits Configurable