ELAP CM 50 Search Results

Elap cm 50

Abstract: ELAP
Contextual Info: HOLTEK r r HT761X General Purpose PIR Controller Features • • • • • • • • Stand-by current: 100|iA Typ. On-chip regu lator A djustable output duration C D S input 40 second warm -up ON/AUTO/OFF selectable by M ODE pin • • Override function

Elap 400

Abstract: SP8647 IN4148 SP8647AC divide-by-10
Contextual Info: SP8647AC 250MHz ^ 10/11 TWO MODULUS DIVIDER CONFORMS TO MIL-STD-883C CLASS B The SP8647 is an ECL variable modulus divider, with ECL 10K and TTL/CM O S com patible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high state and by 11 when both are low (or open circuit).

Contextual Info: L 7C 108/109 mm D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 128K x 8 Static RAM w ith Chip Select Pow erdow n, O utput Enable □ A uto-Pow erdow n Design □ A dvanced CM O S Technology □ High Speed — to 15 ns maximum □ Low Pow er Operation

gps-101

Abstract: LOG RX1 1012 10.1 inch lcd with led backlight 40 pin connector pinout GPS-101-2 5106-4501-000 GPS antenna SV02 SV13 lcd gps nav pinout LCD SERVICE MANUAL
Contextual Info: Global Positioning Simulator GPS-101-2 Operation Manual 1002-1004 -200 Issue - 4 EXPORT CONTROL WARNING: This document contains controlled technology or technical data under the jurisdiction of the Export Administration Regulations EAR , 15 CFR 730-774. It cannot be

Contextual Info: PRELIMINARY 1,048,576 W ORD x 4 BIT DYN AM IC RAM DESCRIPTION T he T C 514410A P /A J/A SJ/A Z is the n e w g en e ra tio n dyn am ic R A M organized 1 ,0 4 8 ,5 7 6 words by 4 bits. T he T C 514410A P /A J/A SJ/A Z u tiliz es T O S H IB A ’S CM OS S ilico n gate process tech n ology as w e ll as

ELAP cm 76

Abstract: 1232B 7174K Sanyu
Contextual Info: SANYO SEMI CONDUCTOR CORP 32E D ? ' i ‘ï 7 0 7 b GOQflQSti. 4 a T -7 7 -2 1 C M O S 1C 1232B Autom atic M usic Selector up to 7 Selections for Tape Recorders T h e LC7517 is a sin g le-ch ip CM OS IC d esig n ed to a u to m a tic a lly s e le c t y o u r d e s ire d m u s ic u p to 7

Contextual Info: , CDP68HC05J4B CDP68HCL05J4B, CDP68HSC05J4B F ebru ary 19 9 7 8-Bit Enhanced Microcontroller Series Features Description The following are som e of the hardware and software highlights of the C D P 68H C 05J4B fam ily of H C M O S M icrocom puters. T he C D P 6 8 H C 0 5 J4 B H C M O S M icro com pu ter is a m em ber

3XXXS

Abstract: IC 7470 pin configuration pin diagram of ic 7470
Contextual Info: M IT S U B IS H I M IC RO CO M PUTERS 7470/7471 Group S IN G L E -C H IP 8 -B IT CM O S M IC R O C O M P U T E R DESCRIPTION The 7470/7471 group is a s in g le -c h ip m icro com p uter d e ­ PIN CONFIGURATION TOP VIEW signed w ith C M O S silicon gate technology. It is housed in a

CI 7478

Abstract: M37477M2-XXXSP Elap cm 74 3122V ELAP cm7
Contextual Info: M IT S U B IS H I MICROCOMPUTERS 7477/7478 Group S IN G L E -C H IP 8 -B IT C M O S M IC R O C O M P U T E R DESCRIPTION The 7477/7478 group is the s in g le -c h ip m icro com p uter d e ­ PIN CONFIGURATION TOP VIEW signed w ith C M O S silicon gate technology.

HD6309

Abstract: hitachi HD6309 HD63B09P HD6309e HD63C09P HD6809E HD6809 HMCS6800 HD63B09 HD63C09
Contextual Info: #U180 HD63B09, HD63C09 CMOS Microprocessing Unit MPU JANUARY, 1988 H IT A C H I Pin A rra n g e m e n t D escrip tion The H D 6309 is th e h ig h est 8 -b it m icro­ p rocessor of H M C S6800 family, w h ich is co m p atib le w ith th e co n v en tion al H D 6809.

Contextual Info: A D E -207-037 O Mar. 1990 Pre lim in a ry - HD 66108T R A M -Provided 165-C hannel LCD Driver for Liquid-Crystal D ot Matrix Graphics H ITA CH I Description T he H D 66108T under control o f an 8-bit M PU can drive a dot m atrix graphic L C D (liquid-crystal

ELAP cm 76

Contextual Info: M IT S U B IS H I MICROCOMPUTERS M 37710M 4BXXXFP S IN G L E -C H IP 1 6-B IT CM O S M IC R O C O M P U T E R DESCRIPTION • In te rru p ts .19 type s 7 levels The M 37710M 4BXXXFP is a sin g le -c h ip m icro com p uter d e ­

M3766

Abstract: M3865 BE 84 CY7C43646AV CY7C43666AV CY7C43686AV CY7C436X6AV
Contextual Info: V CYPRESS CY7C43646AV PRELIMINARY CY7C43666AV/CY7C43686AV 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features Fully a s yn ch ro n o u s and s im u lta n e o u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, first-in first-o u t F IF O

ELAP CM 72

Abstract: Elap 72 concurrent rdram Elap cm 50 rdram concurrent 72M LG rdram 16C LG concurrent RDRAM LG GM73 gm73v
Contextual Info: G M 73V 6484_16C 8 ,3 8 8 ,6 0 8 W O R D S x 8 B IT C M O S D Y N A M IC R A M LG Semicon Co.,Ltd. Description T h e G M 7 3 V 6 4 8 4 H C o n c u rre n t R am b u s D R A M s eries are e x tre m e ly h ig h -s p e e d C M O S D R A M s o rg a n iz e d as 8M

Contextual Info: - ^ n n n > CYPHhbo CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY = 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted Features • H ig h -s p e ed , low -pow er, b id irec tio n al, First-In First-O ut

7730E

Abstract: 7730BN av ct hen ltv EVAL-AD SR-5st 7730C 4-20 led loop powerd circuit diagram pin configuration 7730 IC
Contextual Info: ANALOG DEVICES Bridge Transducer ADC AD7730/AD7730L T h e m o d u la to r o u tp u t is p ro cessed b y a low p a ss program m able d ig ita l filler, allow ing ad jistm e n t o f filte r c u to f f o u tp u t rate an d settling tim e . KEY FEATURES Resolution of 230,000 Counts Pfeak-to-Pfeak

CY7C43646V

Abstract: CY7C43666V CY7C43686V AEB 015 P
Contextual Info: V CYPRESS CY7C43646V CY7C43666V/CY7C43686V PRELIMINARY 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features — Ic c = 60 m A , lSB= 12 m A Fully a s yn ch ro n o u s and s im u lta n e o u s read and w rite o p e ratio n p erm itted • For FWFT Mode, Please See Errata Attached

BO-35

Abstract: CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 BO35 AQ35 bq35
Contextual Info: • CY7C 43622 C Y 7C 43632/C Y 7C 43642 C Y 7C 43662/C Y 7C 43682 ¡o x o w m . m p' rVv^ ' YX xP XR F ^ P R E L IM IN A R Y 256/512/1 K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features F ully as yn ch ro n o u s and sim u ltan eo u s read an d w rite

ELAP CM 72

Abstract: LA 7887 AD7887 X7pa HM005
Contextual Info: ANALOG 2.7Vto 5.25V, Micro Power, Dual-Channel, DEVICES 125 kSPS, 12-Bit ADC in 8-PinpSOIC Preliminary Technical Data AD7887 FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for VDDof 2.7 V to 5.25 V Flexible Power/Throughput Rate Management Shut Down Mode: 1pA max

Contextual Info: CY7C43646V CY7C43666V/CY7C43686V PRELIMINARY 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features Fully a s y n c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, first-in first-o u t F IF O

JDS SB switch

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C43664V/CY7C43684V
Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY CYPRESS 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features — Ic c = 60 m A , lSB= 12 m A F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted FWFT Mode, Ptease See Errata Attached

TRANSISTOR 5101 FG

Abstract: j 13007-2 WM7 SMD transistor marking code MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR TRANSISTOR SMD MARKING CODE s01 smd transistor bq SAA 1025 AHL touch 1015G ELAP cm 76
Contextual Info: NEC USER’S MANUAL J0.PD75518 4 BIT SINGLE-CHIP MICROCOMPUTER HPD75517 X P D 7 5 5 1 8 |iPD75P518 Document No. IEU-1305E (O. D. No. IEU-743E Date Published January 1995 P Printed in Japan F£C Corporation 1990 •I b427SSS 0D^S3EH 174 ■ Cautions on CM OS D evices

TA8862P

Abstract: toshiba ta8862p TA8862
Contextual Info: TOSHIBA TMP87C833/C33/H33 CMOS 8-BIT MICROCONTROLLER T M P 8 7 C 8 3 3 N , TMP87C33IM, T M P 8 7 C H 3 3 N , The 87C833/C33/H33 is th e h ig h speed a n d h ig h p e rfo rm a n c e 8 - b it sin g le c h ip m ic ro c o m p u te r. This MCU c o n ta in s CPU core, ROM, R AM , in p u t/o u tp u t po rts, six m u lti- fu n c tio n tim e r/c o u n te r, serial in te rfa c e , o n ­

Contextual Info: AMD3 18524 70- Novi 996 AM D-K5 Processor Technical Reference M anual 5 Bus Interface This c h a p te r describes two closely re la te d subjects, bus signals (Sections 5.1 and 5.2 and th e bus-cycle protocols im plem en ted w ith those signals (Sections 5.3 and 5.4). T hese sections