ECL 300 Search Results

9434

Abstract: CY101E383 EME-6300H
Contextual Info: Reliability Report QTP# 94346/95255, Version 1.0 June, 1996 BiCMOS ECL-TTL/TTL-ECL TRANSLATOR MARKETING PART NUMBERS DESCRIPTION CY101E383 ECL/TTL/ECL Translator and High Speed Bus Driver CY10E383 ECL/TTL/ECL Translator and High Speed Bus Driver CYPRESS SEMICONDUCTOR

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

Contextual Info: A /D Converter For Industries Instruments Bit Speed MSPS Pd |mW| CXA1076AK P ari Number 8 200 1450 CXAI176AK 8 300 CXA1166K 8 250 Functions P age Flash, ECL I/O 159-174 1450 Flash, ECL I/O 159-174 1700 Flash, ECL I/O 175-186 500 2200 Flash, ECL I/O 187-197

Contextual Info: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

b765

Abstract: PAL 008 PAL10016RD8 PAL1016RD8
Contextual Info: PRELIMINARY September 1986 ECL Registered and Latched Programmable Array Logic PAL Family General Description The registered and latched ECL PAL devices are the latest additions to National Semiconductor's ECL PAL family. The ECL PAL family utilizes National Semiconductor's advanced

SG86A

Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

CAN split termination

Abstract: SG86A SG53A AN1568
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

ecl 10K

Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Contextual Info: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate

XEP56V

Abstract: SY100EP56VK4GTR MC100EP56DT MC100EP56DTR2 SY100EP56V SY100EP56VK4G SY100EP56VK4I SY100EP56VK4ITR
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

XEP56V

Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

marking Ed11

Contextual Info: PECL, ECL, LVDS Page 1 - 6 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products ED1145M ECL Series Full Size Metal Thru-Hole ECL Oscillator Differential or NonDifferential ECL Output without Enable/Disable

XEP57V

Abstract: marking k4 XEP57
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel ECL Pro™ SY100EP57V SY100EP57V FINAL FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time

MC10EP58D

Abstract: MC10EP58DR2 SY100EP58V SY10EP58V SY10EP58VZI SY10EP58VZITR
Contextual Info: ECL Pro SY10EP58V ECL Pro™ SY100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER Micrel, Inc. SY10EP58V SY100EP58V FEATURES • 2:1 PECL/ECL multiplexer ■ Guaranteed AC–performance over temperature/voltage • >3GHz fMAX toggle • <200ps rise/fall time

XEP57V

Contextual Info: 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel, Inc. ECL Pro SY100EP57V ECL Pro™ SY100EP57V FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time

Contextual Info: TIEPAL10016ET6C ECL-TO-TTLIMPACT-X" PAL TRANSLATOR CIRCUIT D3352, OCTOBER 1989 • ECL 100K Programmable Logic with ECL-to-TTL Translation JT PACKAGE TOP VIEW • ECL Control Inputs vcc[ '[ l[ l[ l[ l[ '[ '[ • 3-State TTL Outputs • IMPACT-X“ Process with Reliable

TL 2272 R

Abstract: PAL1016RM4AJC
Contextual Info: ECL PAL10/10016RM4A r% \ ÆM National Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi­ conductor ECL PAL family. The ECL PAL Series-A is char­ acterized by 4 ns maximum propagation delays combinato­

Contextual Info: ECL PAL10/10016RM4A m National ÆM Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi­ conductor ECL PAL family. The ECL PAL Series-A is char­ acterized by 4 ns maximum propagation delays combinato­

Contextual Info: SPST ECL Switches With Drivers 2662 Series V2.00 Features ● ● ● Broadband Frequency Ranges Environmentally Sealed ECL Compatible Description M/A-COM’s Emitter Coupled Logic ECL PIN diode switches offer multi-octave bands from UHF to Ku-band. Advantages of an ECL switch are narrow pulse width

CY101E383

Abstract: E383 E1472
Contextual Info: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL

Contextual Info: TIEPAL10H16ET6C ECL-TO-TTLIMPACT-X PAL TRANSLATOR CIRCUIT D3283, OCTOBER 1989 JT P A C K A G E • ECL10KH Programmable Logic with ECL-to-TTL Translation ECL Control Inputs

Contextual Info: ECL DIGITAL DELAY LINES RESISTORS •CAPS » COILS •DELAY U NES E10 SERIES - ECL10KINTERFACED E100 SERIES - ECL 100K INTERFACED FEATURES □ Industry’s widest selection! □ Economical cost, prompt delivery □ Fast 2nSec rise time typical □ Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

10H645

Abstract: E211 MC10E111 MPC973 AN1405
Contextual Info: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over

Contextual Info: PAL10/10016P8 ECL Programmable Array Logic ECL PAL10/10016P8 National Semiconductor General Description The PAL1016PB/10016P8 is the first member of an ECL programmable logic device family possessing common electrical characteristics, utilizing an easily accommodated

Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL