ECC C T23 Search Results

STP1080

Abstract: ultrasparc 3
Contextual Info: UltraSPARC -! Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-1 Systems D e s c r ip t io n The UDB-I is a data buffer device used in UltraSPARC-1 system s to connect the CPU and its external SRAM cache bus to the system bus: • On the C P U /SR A M side, the E-Cache Bus consists of 128 data bits and 16 parity bits

Sun UltraSparc T2

Abstract: Sun UltraSparc T1 STP1080 sparc v8 spitfire Sun UltraSparc II
Contextual Info: Prel i m i na r y SPA RC T echrdogy STP1080 Business May 1995 UltraSPARC-1 Data Buffer U DB DATA SHEET Revision 0.3 Introduction The UltraSPARC^ Data Buffer(UDB) consists of two chips that connect UltraSPARC-! and its E-eache to a 144bit data bus. Data Buffer chips move data between the E-eache and DataBus. The E-eache data bus, EcacheBus,

STP1080A

Abstract: IEEE1149
Contextual Info: STP1080A July 1997 UltraSPARC -I Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-I Systems DESCRIPTION The UDB-I is a data buffer device used in UltraSPARC-I systems to connect the CPU and its external SRAM cache bus to the system bus:

STP1080ABGA-100

Contextual Info: STP1080A July 1997 UltraSPARC -I Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-I Systems DESCRIPTION The UDB-I is a data buffer device used in UltraSPARC-I systems to connect the CPU and its external SRAM cache bus to the system bus:

Contextual Info: STP1080A S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC -! Data Buffer UDB-I DATA SHEET Companion Device for 167/200 MHz UltraSPARC-I Systems D e s c r ip t io n The UDB-I is a data buffer device used in UltraSPARC-1 system s to connect the CPU and its external SRAM

Liming T78 5v

Abstract: Liming T78 8751 microcontroller controller st506 82C780 68HC11 ST506 ST-506 Chips and Technologies microchannel timing microchannel
Contextual Info: 82C780 Microchanneltm Hard Disk Controller t Prelim in ary D a t a S h e e t January 1989 The Information contained in this document is being issued In advance of the production cycia of this device. The parameters for the device may change before final production. This document is protected by copyright and contains

ultrasparc

Contextual Info: UltraSPARC “-!! Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro­ processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

Contextual Info: S un M icroelectronics O c to b e r 1996 UltraSPARC -!! Data Buffer UDB-II DATA SHEET High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its E-Cache to the slower system data bus. These

Contextual Info: S un M icroelectronics O c to b e r 1996 UltraSPARC -!! Data Buffer UDB-II DATA SHEET High-Capacity, Two-Speed Data Transfer D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical integrated circuit microchips connecting the UltraSPARC-II microprocessor and its E-Cache to the slower system data bus. These

UltraSPARC ii

Contextual Info: i f 4 4 oooo ò o o < »000 ° 00 ° c IO 5 5 o o o < »0000 000 « IOOOO 0 0 ( UltraSPARC-II Data Bujjer (UDB-II Data Sh eet O c t o b e r 1 996 STP1081 S un M ic r o e le c t r o n ic s October 1996 UltraSPARC -II Data Buffer (UDB-II) DATA SHEET High-Capacity, Two-Speed Data Transfer

UltraSPARC ii

Contextual Info: if 4 4 o o oo »000 ° 00 ° c IO 5 5 o »0000 000 « ò o o < o o < IO O O O 00( WËÊIÊÈËÎIËKÊËÊË UltraSPARC-II D ata Buffer (UDB-II Data Sheet October 1996 STP1081 S un M icroelectronics S T P 10 8 1 O c to b e r 1996 »TM UltraSPARC -II Data Buffer (UDB-II)

STP1081

Abstract: 75193 Sun UltraSparc T2 40N20
Contextual Info: STP1081 July 1997 UltraSPARC -II Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems DESCRIPTION The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II microprocessor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

WD10C00

Abstract: WD10C01
Contextual Info: WD10C01 INTRODUCTION 1.0 INTRODUCTION The WD10C01 is a VLSI Winchester/Optical Disk Controller chip that provides the data handling and control for intelligent disk applications. The WD10C01 interfaces to nearly any serial disk in­ terface, including ST412, ST412HP, ESDI, SMD,

Contextual Info: WDWC01 WESTERN D IG IT A L CORP 54E D • 1710526 TABLE OF CONTENTS Section 1.0 2.0 T- 5 2 - 3 3 - 6 3 Title Page INTRODUCTION . 1.1 Features . GENERAL DESCRIPTION G 0 1 S 1 3 0 Ö 10 M ltlD C 21-1 21-1 . . 21-2 3.0

wd10c00

Abstract: winchester wdc 88 Western Digital WD10C01 smd a253 ST412 ST412 120
Contextual Info: WESTERN DIGITAL CORP ODISlB'i GTR 54E T> . \ \ ., r ^ v T r ^ r n jf^rJ .l -,L• ' Í L-■-'■J - - 1-r^~J.'; r »" i X / r ’i ■: / t '/. '4- r V /i "J ^ ■ï r f i 1 ►I*1/ - / ■ v ]p ' ’ \ - s \ - j -% ! i m 1■; r t - v ì T - 5 Z - 3 3 ' l¿>3>

MSB2521

Abstract: 144-GPY2 sds rsl2 BUX 127 5-bf7 67-SD15 BC011 TGS 815 85A7 WD61C96A
Contextual Info: INTRODUCTION WD61C96A 1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION 1.1.3 This document describes a single chip VLSI Peripheral Cache Manager, SCSI bus controller, and Disk Controller device, the WD61C96A, for target mode of operation. The WD61C96A is a highly integrated CMOS VLSI device which

lc7866

Contextual Info: DVD Front End 1C LC78661W Specifications [Preliminary] Functional Description SANYO Electric Co., Ltd. Semiconductor Company System Business Division, Digital A udio Business Unit DVD Front End 1C Preliminary Specifications Contents page 1. Overview . 1

82801DB

Abstract: E8870DH intel 4002 W32 MARKING 82802AC 82870P2 E8870 E8870IO E8870SP P64H2
Contextual Info: Intel E8870IO Server I/O Hub SIOH Datasheet Product Features • ■ ■ ■ ■ ■ ■ Scalability Port (SP): — Two SPs with 3.2 GB/s peak bandwidth per direction per SP. — Bi-directional SPs for a total bandwidth of 12.8 GB/s. Four Hub Interface 2.0 Ports:

GT-64121A

Abstract: RD5B R5000 RC4650 RC5000 RM7000 16M x8 55ns 72 pin flash dimm w01w GT-64120A MIPS R7000
Contextual Info: GT–64121A Galileo System Controller for RC4650/4700/5000 and RM526X/527X/7000 CPUs Datasheet Revision 1.0 MAR 14, 2000 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Integrated system controller with PCI interface

DBL 2028

Abstract: ST412 ST412HP ST506 WD10C01A ST412 120
Contextual Info: WD10C01A TABLE OF CONTENTS Page Section Title 1.0 INTRODUCTION Features 1.1 20-1 20-1 2.0 GENERAL DESCRIPTION 20-2 3.0 SYSTEM BLOCK DIAGRAM 20-3 4.0 SIGNAL DESCRIPTION 20-4 5.0 ARCHITECTURE Error Correction And Detection Codes 5.1 5.1.1 CCID-CRC Reed-Solomon ECC

yx 801

Abstract: yx 801 led STROM RELAIS Relais ECC 85 801 yx STROM RELAIS yx 801 ecc c t23 montage relais
Contextual Info: Zeitrelais Multi-asymmetrischer Taktgeber Typ ECC • • • • • • • • • • • • • • • Produktbeschreibung Dreifach-Funktions-Zeitrelais, asymmetrischer Taktgeber mit individuell wählbaren Zeitbereichen T1 & T2 von 0,1 s bis 100 h.

cmps a42

Abstract: SL357 82459AD mark code t4 diode 82459 A671 transistor cmps a44 cmps A45 82459AC cmps a55
Contextual Info: Pentium II Processor Specification Update Release Date: April 1999 Order Number: 243337-025 The Pentium II processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification

MIPS R7000

Abstract: gt-64120a GT-64111
Contextual Info: GT–64120A Galileo System Controller For RC4650/4700/5000 and RM526X/527X/7000 CPUs Product Preview Revision 1.0 FEB 29, 2000 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Integrated system controller with PCI interface

Contextual Info: 26792 Rev. 3.02 AMD-8132 HyperTransport™ PCI-X 2.0 Tunnel Data Sheet March 2005 AMD-8132™ HyperTransport™ PCI-X® 2.0 Tunnel Product Summary Overview The AMD-8132™ HyperTransport™ PCI-X®2.0 tunnel developed by AMD provides two PCI-X bridges