E-RATE MULTIPLEXER Search Results

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Contextual Info: DATA S H E E T JULY 1999 Revision 2.0 LXT6234 E-Rate Multiplexer General Description Features The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data

M21001

Contextual Info: Quad Multi-Rate CDR with Amplif-Eye 42 Mbps–800 Mbps M21001 The M21001 is a high-performance quad multi-rate > K E Y F E AT U R E S clock and data recovery (CDR) array, optimized for > Four independent multi-rate CDRs running between 42Mbps-800Mbps

circuit diagram of 64-1 multiplexer

Abstract: E1 AMI HDB3 decoder HDB3 Frame structure for Multiplexing of four E2 streams into E3 stream Frame structure for Multiplexing of four E1 streams into E2 stream 16 line to 4 line coder multiplexer SXT6234 multiplexing demultiplexing e2 E1 HDB3 multiplexer/14052B
Contextual Info: DATA SHEET JUNE 1997 SXT6234 REVISION 1.1 E-Rate Multiplexer General Description The SXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data

16 line to 4 line coder multiplexer

Abstract: Frame structure for Multiplexing of four E1 streams into E2 stream LEVEL ONE COMMUNICATIONS LXT6234QE HDB3 Frame structure for Multiplexing of four E2 streams into E3 stream E2 hdb3 HDB3 DECODER E1 AMI HDB3 decoder mais
Contextual Info: DATA SHEET JULY 1999 Revision 2.0 LXT6234 E-Rate Multiplexer General Description Features The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data

multiplexing e1 frame to e3 frame

Abstract: HDB3 E2 SDB6234 HDB3 to nrz 1 into 12 demultiplexer circuit diagram HDB3 decoder 1 into 16 demultiplexer circuit diagram using 1 i multiplexing e2 frame e3 design 16 bit demultiplexer introduction HDB3 can use where
Contextual Info: APPLICATION NOTE 9501 APRIL 1996 SXT6234 E-Rate Multiplexer For 16-E1/E3 Multiplexer/Demultiplexer Introduction 1 E1 Standard The SXT6234 E-Rate Multiplexer offers a simple and economic approach to building E1/E2, E2/E3 and E1/E3 multiplexers and demultiplexers. This application note

BCM8120

Abstract: BCM8121
Contextual Info: BCM8120 PRODUCT Brief MULTI-RATE 10 Gbps 16:1 MULTIPLEXER WITH CLOCK GENERATION B C M 8 1 2 0 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock multiplication unit CMU and multiplexer (MUX) • Multi-rate serial output data and clock • 16:1 multiplexer with LVDS parallel data and clock

BCM8120

Abstract: BCM8121
Contextual Info: BCM8120 PRODUCT Brief MULTI-RATE 10 Gbps 16:1 MULTIPLEXER WITH CLOCK GENERATION B C M 8 1 2 0 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock multiplication unit O F B E N E F I T S compliance with Optical Internetworking Forum • Provides

HD b3c

Contextual Info: APRIL, 1996 SXT6234 E-Rate Multiplexer General Description Features The SXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. A ll of the necessary

16 line to 4 line coder multiplexer

Abstract: LEVEL ONE COMMUNICATIONS circuit diagram of 64-1 multiplexer Frame structure for Multiplexing of four E2 streams into E3 stream 500E SXT6234 HDB3 AMI ENCODER DECODER Frame structure for Multiplexing of four E1 streams into E2 stream multiplexing demultiplexing e2 E1 HDB3
Contextual Info: DATA SHEET AUGUST 1998 Revision 1.3 SXT6234 E-Rate Multiplexer General Description Features • Performs four-E1 to one-E2, or four-E2 to one-E3 multiplexing. Five ICs will implement a sixteen-E1 to one-E3 multiplexer. The SXT6234 E-Rate Multiplexer is a single-chip solution

Contextual Info: BCM8228 PRODUCT Brief VariRateTM MULTI-RATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PM B C M 8 2 2 8 F E AT U R E S Highly integrated rate adaptation device that maps a • single STS-3/STM-1 or a single STS-12/STM-4 stream • • • • • • •

Contextual Info: DATA S H E E T MARCH 1999 Revision 1.1 LXP610 Low-Jitter Multi-Rate Clock Adapter CLAD General Description Features The LXP610 Multi-Rate Clock Adapter (CLAD) offers pin-selectable frequency conversion between T1 and E l rates as well as 8 additional rates from 1.544 MHz to

E1 HDB3

Abstract: 16 line to 4 line coder multiplexer HDB3 to nrz HDB3 AMI ENCODER DECODER Frame structure for Multiplexing of four E2 streams into E3 stream circuit diagram of 64-1 multiplexer NOTES ON MULTIPLEXER nrz to hdb3 E2 hdb3 HDB3 decoder
Contextual Info: 6234_4.fm4 Page 1 Wednesday, June 12, 1996 4:32 PM DATA SHEET APRIL, 1996 SXT6234 E-Rate Multiplexer 1 General Description Features The SXT6234 E-Rate Multiplexer is a single-chip solution for multi plexi ng four tri butary channels into a single high speed data stream and for demultiplexing a high speed data

Contextual Info: BCM8130 PRODUCT Brief MULTI-RATE 10 Gbps 16:1 MUX WITH CLOCK GENERATION B C M 8 1 3 0 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock multiplication unit CMU and multiplexer (MUX) • Support for multiple rates — OC-192: 9.953 Gbps,

PB02

Abstract: BCM8130 BCM8131 "network interface cards"
Contextual Info: BCM8130 PRODUCT Brief MULTI-RATE 10 Gbps 16:1 MUX WITH CLOCK GENERATION B C M 8 1 3 0 S U M M A R Y F E AT U R E S Fully integrated multi-rate clock multiplication unit • CMU and multiplexer (MUX) Support for multiple rates — OC-192: 9.953 Gbps, • OC-192

HDB3 AMI ENCODER DECODER

Abstract: multiplexing e1 frame to e3 frame Frame structure for Multiplexing of four E2 streams into E3 stream LXT6234QE HDB3 to nrz multiplexer 30 pin circuit diagram of 64-1 multiplexer HDB3 intel 4e2 E1 HDB3
Contextual Info: LXT6234 E-Rate Multiplexer Datasheet The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. All of the necessary circuitry is integrated into the LXT6234 ERate Multiplexer; there is no need for an external framing device.

21012-BRF-001-B

Abstract: M21012 M21001 M21011
Contextual Info: Quad Multi-Rate CDR with Amplif-Eye 42 Mbps – 3.2 Gbps M 2 1 0 1 2/1 1/01 The M21012/11/01 are high-performance quad multi- > K E Y F E AT U R E S rate clock and data recovery (CDR) arrays, optimized for multi-lane telecom and datacom applications. Each CDR

M21012

Abstract: DSA004886
Contextual Info: Quad Multi-Rate CDR with Amplif-Eye 42 Mbps – 3.2 Gbps M21012 The M21012 is a high-performance quad multi-rate > K E Y F E AT U R E S clock and data recovery (CDR) array, optimized for multi-lane telecom, datacom, and video applications. Each CDR operates independently at bit rates between

Contextual Info: LF43881 8 x 8-bit Digital Filter D E V IC E S IN C O R P O R A T E D FEATURES □ □ □ □ 25 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or Two's Complement Data □ 8-bit Unsigned or Two's Complement Coefficients

M21011

Contextual Info: Quad Multi-Rate CDR with Amplif-Eye 1 Gbps – 3.2 Gbps M21011 The M21011 is a high-performance quad multi-rate > K E Y F E AT U R E S clock and data recovery (CDR) array, optimized for multi-lane telecom, datacom, and video applications. Each CDR operates independently at bit rates between

Contextual Info: LF43891 9 x 9-bit Digital Filter D E V IC E S IN C O R P O R A T E D □ □ □ □ 40 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data/Coefficients □ 26-bit Data Outputs □ Shift-and-Add Output Stage for

Contextual Info: Standard Product February, 1994 LXP610 Low-Jitter Multi-Rate Clock Adapter CLAD Gert&raJ Description Features The LXP610 Multi-Rate Clock Adapter (CLAD) offers pinselectable frequency conversion between T1 and E l rates as • Translates between 10 different frequencies.

BCM8120

Abstract: BCM8121
Contextual Info: BCM8121 PRODUCT Brief MULTI-RATE 10 Gbps 1:16 DEMULTIPLEXER WITH CDR B C M 8 1 2 1 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock and data recovery CDR and demultiplexer (DEMUX) • 1:16 DEMUX with LVDS parallel data and clock outputs

la 7680

Contextual Info: Standard Product February, 1994 LXP610 Low-Jitter Multi-Rate Clock Adapter CLAD Features The LXP610 Multi-Rate Clock Adapter (CLAD) offers pinselectable frequency conversion between T1 and E l rates as well as 8 additional rates from 1.544 MHz to 8.192 MHz.

Contextual Info: BCM8121 PRODUCT Brief MULTI-RATE 10 Gbps 1:16 DEMULTIPLEXER WITH CDR B C M 8 1 2 1 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock and data recovery CDR and demultiplexer (DEMUX) • 1:16 DEMUX with LVDS parallel data and clock outputs