E CLOCK AND DATA RECOVERY CDR Search Results

Contextual Info: BCM8711 PRODUCT Brief 10GE 1:16 DEMULTIPLEXER WITH CLOCK AND DATA RECOVERY B C M 8 7 1 1 S U M M A R Y F E AT U R E S • IEEE 802.3ae 10.3125-Gbps Ethernet deserializer with clock and data recovery CDR and demultiplexer (DEMUX) • 1:16 demultiplexer with LVDS 644.55-Mbps data outputs

specifications for oc-48 of edfa amplifier

Abstract: sis 650 MAX3745 MAX3861 MAX3872 MAX3872EGJ OC-24
Contextual Info: 19-2709; Rev 0; 1/03 KIT ATION EVALU E L B A IL AVA Multirate Clock and Data Recovery with Limiting Amplifier Features The MAX3872 is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48, OC-48 with FEC SONET/SDH and Gigabit

sis 650

Abstract: MAX3745 MAX3861 MAX3872 MAX3872EGJ OC-24
Contextual Info: 19-2709; Rev 1; 5/03 KIT ATION EVALU E L B A IL AVA Multirate Clock and Data Recovery with Limiting Amplifier Features The MAX3872 is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48, OC-48 with FEC SONET/SDH and Gigabit

TA8101

Abstract: TA8105 passive loopthrough PS 224 ETF-8103 TQ8103 TQ8103-Q TQ8105
Contextual Info: J R I Q li I N T S E M I C O N D U C T O R , I N C 7PS1 The TQ8103 is a monolithic clock and data recovery CDR IC that receives TQ8103 NRZ data, extracts the high-speed clock, and presents the separated data and clock as its outputs. This device is designed specifically for SONET

ETF-8103

Abstract: TQ8103 TQ8103-Q TQ8105 passive loopthrough
Contextual Info: R I Q U I N T S E M I C O N D U C T O R, I N C . The TQ8103 is a monolithic clock and data recovery CDR IC that receives NRZ data, extracts the high-speed clock, and presents the separated data and clock as its outputs. This device is designed specifically for SONET

flip-flop

Contextual Info: Data Sheet February 1997 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations LG1600FXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design

regenerator

Abstract: LG1600AXD LG1600FXH LG1600FXH0553 LG1600FXH0622 LG1600FXH2488 LG1605DXB TF1004A
Contextual Info: Data Sheet February 1997 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations LG1600FXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design

Contextual Info: 19-2710; Rev 4; 7/06 KIT ATION EVALU E L B A AVAIL 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier Features ♦ 2.488Gbps and 2.667Gbps Input Data Rates ♦ Reference Clock Not Required for Data Acquisition ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH

Contextual Info: BCM8121 PRODUCT Brief MULTI-RATE 10 Gbps 1:16 DEMULTIPLEXER WITH CDR B C M 8 1 2 1 S U M M A R Y F E AT U R E S • Fully integrated multi-rate clock and data recovery CDR and demultiplexer (DEMUX) • 1:16 DEMUX with LVDS parallel data and clock outputs

CAZ MARKING

Abstract: sis 315 MAX3745 MAX3874 MAX3874AEGJ MAX3874EGJ T2055-4
Contextual Info: 19-2710; Rev 3; 1/05 KIT ATION EVALU E L B A IL AVA 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier Features ♦ 2.488Gbps and 2.667Gbps Input Data Rates ♦ Reference Clock Not Required for Data Acquisition ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH

Contextual Info: Data Sheet June 1999 m ic r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations LG1600KXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply ■ Robust FPLL design

Contextual Info: p r io r it y Data Sheet February 1997 m ic r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations LG1600FXH Clock and Data Regenerator Features • Integrated clock recovery and data retiming ■ Surface-mount package ■ Single ECL supply

Contextual Info: R I 1 Q Q U & I N S E M I C O N D U C T O R , I N C T ÎI The TQ8103 is a monolithic clock and data recovery CDR IC that receives TQ8103 NRZ data, extracts the high-speed clock, and presents the separated data OC-12 and SDH STM-4 applications at 622 Mb/s.

GR-1377-CORE

Abstract: Si5364 Si5530 STM-64 K810
Contextual Info: Si5530 P R E L I M I N A R Y D A TA S H E E T SiPHY OC-192/STM-64 SONET/SDH R ECEIVER Features Complete low power, high speed, receiver with integrated limiting amplifier, clock and data recovery CDR , and 1:16 demultiplexer: Data Rates Supported: OC-192/

M21050

Contextual Info: Duplex Quad Octal Multi-Rate CDR with Amplif-Eye (1.0 Gbps - 3.2 Gbps) M21050 The M21050 is a high-performance duplex quad (octal) > K E Y F E AT U R E S multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom and datacom applications.

8 bit ttl mux

Abstract: pin diagram of mux FOA21002A1 FOA41001B1 FOA41002B1 FOA51001B1 FOA51002B1 OIF99 foa3100
Contextual Info: P R O D U C T B R I E F Semiconductor Solutions for High Speed Communication and Fiber Optic Applications FOA41001B1 16:1 Multiplexer with Clock Multiplication Unit Chip MUX 9.95 - 10.7 Gbit/s, 3.3 V FOA51001B1 1:16 Demultiplexer with Clock and Data Recovery Chip

g 995

Abstract: FOA21002A1 FOA41001B1 FOA41002B1 FOA51001B1 FOA51002B1 fifo ttl 8 bit ttl mux foa3100
Contextual Info: P R O D U C T B R I E F Semiconductor Solutions for High Speed Communication and Fiber Optic Applications FOA41001B1 16:1 Multiplexer with Clock Multiplication Unit Chip MUX 9.95 - 10.7 Gbit/s, 3.3 to 5.0 V FOA51001B1 1:16 Demultiplexer with Clock and Data Recovery Chip

dell monitor circuit diagram

Abstract: DVI TMDS PCB design guidelines dell 2000fp monitor Dell 2000fp ISL54105 ISL54105A ISL54105CRZ TB379 DVI RECEIVER PCB design guidelines
Contextual Info: ISL54105 Key Features S DESIGN W E N R O NDED F COMME E ISL54105A E R T O N Data Sheet SEE T H June 11, 2008 FN6723.0 TMDS Regenerator Features The ISL54105 is a high-performance TMDS timing regenerator containing a programmable equalizer and a clock data recovery CDR function for each of the 3 TMDS

CX20462

Abstract: CX20464
Contextual Info: A CONEXANT BUSINESS 3.2 Gbps Quad Clock and Data Recovery CX20464 The CX20464 is used to retime signals in large switch > K E Y F E AT U R E S matrices. CDRs are critical elements in the SONET/SDH > Low-power 3.3 V and 2.5 V > SmartCenter™ CDR operation (power dissipation

BCM8111

Abstract: BROADCOM "heat sink"
Contextual Info: BCM8111 PRODUCT Brief 9.953-Gbps INTEGRATED LOW POWER SONET/SDH RECEIVER B C M 8 1 1 1 F E AT U R E S • 9.95328-Gbps SONET/SDH receiver • Fully integrated deserializer/demultiplexer DEMUX with clock and data recovery (CDR) circuit. • 1:16 DEMUX with LVDS 622.08-Mbps data outputs

Contextual Info: BCM8111 PRODUCT Brief 9.953-Gbps INTEGRATED LOW POWER SONET/SDH RECEIVER B C M 8 1 1 1 F E AT U R E S • 9.95328-Gbps SONET/SDH receiver • Fully integrated deserializer/demultiplexer DEMUX with clock and data recovery (CDR) circuit. • 1:16 DEMUX with LVDS 622.08-Mbps data outputs

MAX3664

Abstract: MAX3675 MAX3675ECJ
Contextual Info: 19-1258; Rev 1; 10/97 KIT ATION EVALU E L B AVAILA 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier _Features ♦ Single +3.3V or +5.0V Power Supply _Applications _Ordering Information

21012-BRF-001-B

Abstract: M21012 M21001 M21011
Contextual Info: Quad Multi-Rate CDR with Amplif-Eye 42 Mbps – 3.2 Gbps M 2 1 0 1 2/1 1/01 The M21012/11/01 are high-performance quad multi- > K E Y F E AT U R E S rate clock and data recovery (CDR) arrays, optimized for multi-lane telecom and datacom applications. Each CDR

Contextual Info: e n ts fo r io n s Clock and data recovery CDR devices are a key ele­ function have been delineated in both Bellcore TRment of any telecom/datacom system. As data signals NWT-000499 and ITU-T G.958. propagate through a system, signal dispersion and noise degrade the signal and if not properly filtered,