DS101012 Search Results

74FO4

Abstract: ds1010-100 74LS DS1010 DS1010-125 DS1010-150 DS1010-50 DS1010-60 DS1010-75 DS1010-80
Contextual Info: DS1010 10-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable, low profile

DS1868

Abstract: LM 4440 AUDIO AMPLIFIER CIRCUIT DS1230y-200 battery date codes circuit diagram laptop motherboard Scans-049 texas instrument catalog 74ls DS1666-50 st c031 s1040 diode
Contextual Info: S ystem E x t e n s i o n Data Book CPU Supervisors Digital Potentiometers Silicon Timed Circuits Thermal Products DALLAS SEMICONDUCTOR Copyright 1994 Dallas Semiconductor Corporation, Dallas, Texas All Rights Reserved. Circuit diagrams are included to illustrate typical semiconductor applications. Complete information sufficient for

DS1010-500

Abstract: 56-G4009-001B 74FO4 DS1010-125
Contextual Info: DS1010 10-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable, low profile

74ls gate symbols

Abstract: 74FO4 pin diagram of 74LS "Delay Lines" 74ls series 74LS SERIES cmos logic data DS1010-60 74LS series datasheet 74ls series logic DS1010-200
Contextual Info: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater

Contextual Info: DS 1010 DS1010 DALLAS 10 s e m ic o n d u c t o r ~T a P Silicon D elay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN1 £ 1 • 10 taps equally spaced KOI 14 ] Vcc NC[ 2 13 ] TAP 1 in C 1 • Delays are stable and precise TAP 2 ^ 3 12 ] TAP 3

74LS

Abstract: DS1010 DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S ds1010-500
Contextual Info: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater

Contextual Info: 081010 DS1010 DALLAS SEMICONDUCTOR 10-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN1 £ 1 14 ] V CC N C [ 2 13 ] TAP 1 TAP2 C 3 12 ] TAP 3 • Leading and trailing edge accuracy TAP 4 £ 4 11 ] TA P 5 • Delay tolerance ±5% or +2 ns, whichever is greater

Contextual Info: DS 1010 DS1010 DALLAS SEMICONDUCTOR 10-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN1 [ " ^3 7 ] vcc • 10 taps equally spaced • Delays are stable and precise NC c ] TAP 1 TAP 2 C ] TAP 3 ] TAP 5 ] TAP 7 TAP 4 C 1 TAP 9 TAP 6 d

ds1010-100

Abstract: 74LS DS1010 DS1010-125 DS1010-150 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S
Contextual Info: DS1010 10-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable, low profile

Contextual Info: DS1010 DALLAS SEMICONDUCTOR DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 10 taps equally spaced C 1 NcC 2 in • Delays are stable and precise • Leading and trailing edge accuracy ncE 3 TAP 2 [I 4 • Delay tolerance ±5% or ±2 ns, whichever is greater

Contextual Info: DALLAS SEMICONDUCTOR FEATURES D S 10 10 10-Tap Silicon Delay Line PIN A S S IG N M E N T • All-silicon time delay • 10 taps equally spaced • Delays are stable and precise • Leading and trailing edge accuracy • Delay tolerance ±5% or ±2 ns, whichever is greater

74LS

Abstract: DS1010 DS1010-50 DS1010-60 DS1010-75 DS1010G DS1010S
Contextual Info: DS1010 DALLAS SEMICONDUCTOR DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 10 taps equally spaced C 1 NcC 2 in • Delays are stable and precise • Leading and trailing edge accuracy ncE 3 TAP 2 [I 4 • Delay tolerance ±5% or ±2 ns, whichever is greater

Contextual Info: DALLAS SEMICONDUCTOR DS1010 10-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay • 10 taps equally spaced • Delays are stable and precise IN1 [ 1 14 Nc r 2 13 ] TAP 1 TAP2[ 3 12 ] TAP 3 11 ] TAP 5 ] V cc • Leading and trailing edge accuracy

74LS

Abstract: DS1010 DS1010-100 DS1010-125 DS1010-150 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S
Contextual Info: DS1010 10-Tap Silicon Delay Line www.dalsemi.com PIN ASSIGNMENT All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable, low profile