DRAM 1M X 8 Search Results
DRAM 1M X 8 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| CDCV857ADGGR |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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| CDCV857ADGGG4 |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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| CDCV857ADGG |
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2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 |
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| CDCVF2505DR |
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PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode 8-SOIC -40 to 85 |
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| CDCVF2505PWRG4 |
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PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode 8-TSSOP -40 to 85 |
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DRAM 1M X 8 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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333z
Abstract: 333z capacitor 00A80
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OCR Scan |
STI91OOOA STI91000A-60 STI91000A-70 STI91000A-80 110ns 130ns 150ns 30-PIN STI91000A STI91 333z 333z capacitor 00A80 | |
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Contextual Info: KMM5321204AW ELECTRONICS DRAM Module KMM5321204AW/AWG EDO Mode 1Mx32 DRAM SIM M , 5V, 1K Refresh using 1M x 16 DRAM GENERAL DESCRIPTION FEATURES The Samsung KMM5321204AW is a 1M bit x 32 Dynamic RAM high density memory module. The Samsung KMM5321204AW consists of two CMOS |
OCR Scan |
KMM5321204AW KMM5321204AW/AWG 1Mx32 KMM5321204AW 1Mx16bit 42-pin 72-pin | |
A43L2616AContextual Info: A43L2616A Preliminary 1M X 16 Bit X 4 Banks Synchronous DRAM Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue November 30, 2004 Preliminary November, 2004, Version 0.0 |
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A43L2616A A43L2616A | |
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Contextual Info: •HYUNDAI SEMICONDUCTOR HYM581000 Series 1M X 8-bit CMOS DRAM MODULE DESCRIPTION The HYM581000 is a 1M x 8-bit Fast page mode CMOS DRAM module consisting of eight HY531000 In 20/26 pin SOJ on a 30 pin glass-epoxy printed circuit board. 0.22pF decoupling capacitor is mounted for each DRAM. |
OCR Scan |
HYM581000 HY531000 HYM581000M 1BB01-11-MAY93 4L750afl HYM581000M 1BB01-11-M HYM581000A | |
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Contextual Info: UG6M13601PTCT-6 Data sheets can be downloaded at www.unigen.com 4M Bytes 1M x 36 bits FPM MODE DRAM MODULE FPM Mode 72 Pin SIMM w/Parity based on 2 pcs 1M x 16 & 4 pcs 1M x 1 DRAM with LVTTL, 1K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 72-Pin SIMM |
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UG6M13601PTCT-6 1000mil) UG6M13601PTCT-6 UG6DQ26 | |
GM71C4400BJ
Abstract: GM71C4400 GM71C1000 GM71C4 GMM791000
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OCR Scan |
GMM791000BNS GM71C4400BJ, GM71C1000BJ, GMM791000BNS GM71C4400BJ GM71C4400 GM71C1000 GM71C4 GMM791000 | |
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Contextual Info: UG6M13601PBCT-6 Data sheets can be downloaded at www.unigen.com 4M Bytes 1M x 36 bits FPM MODE DRAM MODULE FPM Mode 72 Pin SIMM w/Parity based on 2 pcs 1M x 16 & 4 pcs 1M x 1 DRAM with LVTTL, 1K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 72-Pin SIMM |
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UG6M13601PBCT-6 1000mil) UG6M13601PBCT-6 | |
A43P26161
Abstract: A43P26161V
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A43P26161 133MHz 105MHz A43P26161 A43P26161V | |
A43L1616
Abstract: A43L1616V
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A43L1616 54-pin A43L1616 A43L1616V | |
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Contextual Info: K4S641632E CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Dec. 2000 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.0 Dec. 2000 K4S641632E CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM |
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K4S641632E 64Mbit 16Bit A10/AP | |
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Contextual Info: K4S641632D CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Jun. 1999 K4S641632D CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM |
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K4S641632D 64Mbit 16Bit A10/AP | |
i3 processor
Abstract: A43L2632
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A43L2632 i3 processor A43L2632 | |
K4S641632E-TC75Contextual Info: K4S641632E CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.2 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.2 Sept. 2001 K4S641632E CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM |
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K4S641632E 64Mbit 16Bit K4S641632E A10/AP K4S641632E-TC75 | |
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Contextual Info: HYUNDAI SEMICONDUCTOR HYM581000C Series 1M X 8 -b it CMOS DRAM MODULE DESCRIPTION The HYM581000C is a 1M x 8-bit Fast page mode CMOS DRAM module consisting of eight HY531000A in 20/26 pin SOJ on a 30 pin glass-epoxy printed circuit board. 0.22/iF decoupling capacitor is mounted for each DRAM. |
OCR Scan |
HYM581000C HY531000A 22/iF HYM581000CM/CLM 1BB07-10-M G0Q174S DDQ17M3 | |
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A43P26161
Abstract: A43P26161V
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A43P26161 133MHz 105MHz A43P26161 A43P26161V | |
A43E26161Contextual Info: A43E26161 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM Document Title 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue September 13, 2004 Preliminary 1.0 Final version release December 15, 2004 |
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A43E26161 A43E26161 | |
A43L1616
Abstract: A43L1616V
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A43L1616 A43L1616 A43L1616V | |
A43E16161
Abstract: A43E16161V
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A43E16161 54-pin A43E16161 A43E16161V | |
A43E16161
Abstract: A43E16161V
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A43E16161 A43E16161 A43E16161V | |
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Contextual Info: UG41W641 4 6GSG Data sheets can be downloaded at www.unigen.com 8M Bytes (1M x 64 bits) EDO MODE DRAM MODULE EDO Mode Unbuffered SODIMM based on 4 pcs 1M x 16 DRAM with LVTTL, 1K & 4K Refresh GENERAL DESCRIPTION PIN ASSIGNMENT (Front View) 144-Pin SODIMM FEATURES |
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UG41W641 144-Pin 050mil) | |
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Contextual Info: DRAM MODULE KMM5321204AW/AWG KMM5321204AW/AWG EDO Mode 1Mx32 DRAM SIMM, 5V, 1K Refresh using 1M x 16 DRAM G ENERAL DESCRIPTIO N FEATURES The Samsung KMM5321204AW is a 1M bit x 32 Dynamic RAM high density memory module. The • Part Identification - KMM5321204AW 1024 cycles/16 ms Ref, SOJ, Solder |
OCR Scan |
KMM5321204AW/AWG KMM5321204AW/AWG 1Mx32 KMM5321204AW KMM5321204AW cycles/16 KMM5321204AWG 1Mx16bit | |
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Contextual Info: A43E26162 Preliminary 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM Document Title 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue June 23, 2005 Preliminary 0.1 Modify tSS from 3ns to 2ns July 11, 2005 |
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A43E26162 | |
A43L2616
Abstract: A43L2616V
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A43L2616 166MHz 143MHz 183Mhz 183Mhz A43L2616 A43L2616V | |
A43L2616
Abstract: A43L2616V 1M x 16-Bit x 4 Banks synchronous DRAM
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A43L2616 166MHz 143MHz 183Mhz 183Mhz A43L2616 A43L2616V 1M x 16-Bit x 4 Banks synchronous DRAM | |