DIODE ZH 22 Search Results

Contextual Info: SKT 760 THYRISTOR BRIDGE,SCR,BRIDGE Capsule Thyristor Line Thyristor SKT 760 Features # $%&'% * '%(+, *+-% .)(/ *%&+')* # # # # )0-1,+(2& 3+4-1,% 4+*5+6% 72& 8219,% -)8%8 *22,)06 :/+,2. 8%-)60 .)(/ -)06,% -)8%8 *22,)06 ;0(%&0+()20+, -(+08+&8 *+-% <77=-(+(% +08 &%>%&-% >2,(+6%- 14

Contextual Info: SKT 551 THYRISTOR BRIDGE,SCR,BRIDGE Capsule Thyristors Thyristors SKT 551 Features # $%&'% * '%(+, *+-% .)(/ *%&+')* # # # # )0-1,+(2& 3+4-1,% 4+*5+6% 72& 8219,% -)8%8 *22,)06 :/+,2. 8%-)60 .)(/ -)06,% -)8%8 *22,)06 ;0(%&0+()20+, -(+08+&8 *+-% <77=-(+(% +08 &%>%&-% >2,(+6%- 14

Contextual Info: SKT 491 THYRISTOR BRIDGE,SCR,BRIDGE Capsule Thyristor Line Thyristor SKT 491 Features # $%&'% * '%(+, *+-% .)(/ *%&+')* # # # # )0-1,+(2& 3+4-1,% 4+*5+6% 72& 8219,% -)8%8 *22,)06 :/+,2. 8%-)60 .)(/ -)06,% -)8%8 *22,)06 ;0(%&0+()20+, -(+08+&8 *+-% <77=-(+(% +08 &%>%&-% >2,(+6%- 14

LA1460

Abstract: 2912 sp MA2911 LA1461
Contextual Info: HYBRID I.C.s "Hi-Net" High-speed switching diode arrays and high voltage-w ithstand diode arrays are of NICHICO N's standard series. T hey are com bined to be co nveniently used fo r both binary and decim al system s. High-speed series is ideal fo r co m p u te r peripherals, control boards and general

A2906

Abstract: A2911 A2907 a2902 A0432 MA0429
Contextual Info: HYBRID I.C.s “Hi-Net” Diode Arrays H ig h -s p e e d s w itc h in g d io d e arrays a n d h ig h C O N 's s ta n d a n d series. They are c o m b in e d d e c im a l system s. H ig h -s p e e d series Is idea l g e n e ra l e le c tro n ic a p p lia n c e s . B esides, h ig h

A0651

Abstract: MA2401 AX. A431
Contextual Info: HYBRID I.C.s “H i-Net” Diode Arrays im H ig h - s p e e d s w it c h i n g d io d e arrays a n d h ig h v o lt a g e - w it h s l a n d C O N ' s s t a n d a n d se ries. T h e y are c o m b i n e d d e c im a l s yste m s H ig h -s p e e d general e le c tro n ic

HD74LVCZ240A

Abstract: DSA003634
Contextual Info: HD74LVCZ240A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-229A Z 2nd. Edition February 1999 Description The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

Hitachi DSA002744

Contextual Info: HD74LVCZ245A Octal Bidirectional Transceivers with 3–state Outputs ADE-205-228A Z 2nd. Edition February 1999 Description The HD74LVCZ245A has eight buffers with three state outputs in a 20 pin package. When (T / R) is high, data flows from the A inputs to the B outputs, and when (T / R) is low, data flows from the B inputs to the

HD74LVCZ240A

Abstract: Hitachi DSA00229
Contextual Info: HD74LVCZ240A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-229A Z 2nd. Edition February 1999 Description The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

Contextual Info: HD74LVCZ240A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-229A Z 2nd. Edition February 1999 Description The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

HD74LVCZ245A

Abstract: Hitachi DSA00229
Contextual Info: HD74LVCZ245A Octal Bidirectional Transceivers with 3–state Outputs ADE-205-228A Z 2nd. Edition February 1999 Description The HD74LVCZ245A has eight buffers with three state outputs in a 20 pin package. When (T / R) is high, data flows from the A inputs to the B outputs, and when (T / R) is low, data flows from the B inputs to the

HD74ALVCHS162830

Abstract: DSA003634
Contextual Info: HD74ALVCHS162830 1-bit to 2-bit Address Driver with 3-state Outputs ADE-205-221 Z Preliminary 1st. Edition July 1998 Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V V CC operation. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the

HALF WAVE RECTIFIER 45 E 57

Abstract: HALF WAVE 45 E 57 20-C1V D-68623 HTZ280H20K HTZ280H24K HTZ280H28K HTZ280H32K diode rectifier
Contextual Info: HTZ280H Series LARONTROL High Voltage Diode Rectifier Module IF AV = 4.7 A VRRM = 32000 V Type Number Repetitive Peak Minimum Avalanche Voltage V(BR)R HTZ280H32K HTZ280H28K HTZ280H24K HTZ280H20K 32000 28000 24000 20000 34000 30000 26000 22000 CIRCUIT DIAGRAM

Contextual Info: HTZ280H Series LARONTROL High Voltage Diode Rectifier Module IF AV = 4.7 A VRRM = 32000 V Type Number Repetitive Peak Minimum Avalanche Voltage V(BR)R HTZ280H32K HTZ280H28K HTZ280H24K HTZ280H20K 32000 28000 24000 20000 34000 30000 26000 22000 CIRCUIT DIAGRAM

ADE-205-354

Abstract: Hitachi DSA0076 HD74LV245A HD74LV2G245A
Contextual Info: HD74LV2G245A Dual Bus Transceivers with 3–state Outputs ADE-205-354 Z 1st. Edition May 2000 Description The HD74LV2G245A has two buffers with three state output in a 8 pin package. When DIR is high, data is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs

Hitachi DSA002744

Contextual Info: HD74LVCZ240A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-229 Z Preliminary 1st. Edition December 1998 Description The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1* and 2*). Each enable independently controls

HD74LV125A

Abstract: HD74LV1G125A Hitachi DSA0015
Contextual Info: HD74LV1G125A Bus Buffer Gate with 3–state Output ADE-205-323B Z 3rd. Edition April 2000 Description The HD74LV1G125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up

HD74LV126A

Abstract: HD74LV1G126A Hitachi DSA0015
Contextual Info: HD74LV1G126A Bus Buffer Gate with 3–state Output ADE-205-324B Z 3rd. Edition April 2000 Description The HD74LV1G126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up

Hitachi DSA0076

Abstract: HD74LV240A HD74LV2G240A
Contextual Info: HD74LV2G240A Dual Bus Buffer Inverted with 3–state Output ADE-205-349 Z 1st. Edition May 2000 Description The HD74LV2G240A has dual bus buffer inverted with 3–state output in a 8 pin package. Two inverters are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE or 2OE,

Hitachi DSA0076

Abstract: HD74LV126A HD74LV2G126A
Contextual Info: HD74LV2G126A Dual Bus Buffer with 3–state Output ADE-205-348 Z 1st. Edition May 2000 Description The HD74LV2G126A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up or

TM 1628 IC

Abstract: TM 1628 IC TM 1628 Datasheet TM 1628 Datasheet TM 1628 IC data sheet LZ GBA HD74BC623A DSA003731 Hitachi DSA003731
Contextual Info: HD74BC623A Octal Bus Transceivers With 3 State Outputs ADE-205-025 Z Rev.0 June 1993 Description The HD74BC623A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5

TM 1628

Abstract: GAB 730 IC TM 1628 Datasheet TM 1628 Datasheet TM 1628 IC LZ GBA TM 1628 IC data sheet HD74BC620A Hitachi DSA003741
Contextual Info: HD74BC620A Octal Bus Transceivers With 3 State Outputs ADE-205-024 Z Rev. 0 June 1993 Description The HD74BC620A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5

diode 1n3433

Abstract: 1N3463 1N3433 1N3580 IN3497 1N3392 IN3646 1N3584 1N3350 1N3432
Contextual Info: co E sw. Zener Type No. e > “ w " S 0« X 5 IN. Ó s Q IN Ó* Q $ E o in CM * E O 5 in cv $ E O a « O N° oN in n n <*» <* ? ^ S . Ss sO 0s- o ' CO ^0 o o o ? ^ \ \ is is fs < X' o d d ' O O"-^ 3 oN oN in xP CO oN in cm «h O o'\0 o o o o ^ 0s O 9 9 9 9 9

Hitachi DSA0076

Abstract: HD74LV2G125A HD74LV125A
Contextual Info: HD74LV2G125A Dual Bus Buffer with 3–state Output ADE-205-347 Z 1st. Edition May 2000 Description The HD74LV2G125A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or