DESTINATION OF IC Search Results

60nd02

Abstract: D0798 D05103 50MHZ S2020 S2021 d2059 DAT02 DAT06 DAT04
Contextual Info: DEVICE HIPPI SPECIFICATION SOURCE/DESTINATION INTERFACE CIRCUITS HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS FEATURES S2020/S2021 HIPPI Chipset • Functionally compliant with the ANSI HIPPI standard • 32-Bit data channel • Equivalent single channel rate of 800 Mbits/sec

3RG7857-1BD

Abstract: 3RG7855-1RG 3RG787-1BD 7855-2BD AlMgSi0,5 ir sensors Siemens Optical Sender ALU-2509 3rg7857 3RG7855-1R
Contextual Info: SIMATIC FS100 3RG7855-XXX MO NTAGEANLEITUNG MOUNTING INSTRUCTION Bestimmung Destination Diese Anleitung beschreibt die Montage und den Aus- These instruction describes mounting and the substitution tausch von Einzelkomponenten der SIMATIC FS100 of single components of the SIMATIC FS100 safety

VAA33

Abstract: AA36 ZSF200
Contextual Info: Switch Fabric Data Sheet 89TSF552 Preliminary Information* Description is configurable up to OC-192. Always non-blocking architecture across destination, traffic type cell, packet , and class of service (CoS). ◆ Supports up to 4 egress subports per switch port.

TU700

Contextual Info: Products for Video Equipment Tuners for TV/VCR/CATV TV Tuner TU700 Series for color TV and VCR •T U 7 0 0 Series Specification of each destination of PAL, JPN and USA are available. Point of input terminal and arrangement of pin for tuner are based on the industry standard.

Contextual Info: 89TSF552 Switch Fabric Data Sheet Preliminary Information* Description is configurable up to OC-192. Always non-blocking architecture across destination, traffic type cell, packet , and class of service (CoS). ◆ Supports up to 4 egress subports per switch port.

001C

Abstract: 68B4
Contextual Info: APPLICATION NOTE H8/300L Super Low Power Series Block Transfer 2: Example Usage of the EEPMOV Instruction MOVE2 Introduction The software MOVE2 moves a block of data from one data memory area to another. Data can be moved even where the source data memory area overlaps the destination data memory area. This is an example of the application software

coin slot

Abstract: "magnetic tape"
Contextual Info: Advanced Micro Devices AN-149 First-In First-Out Memories: Operations and Applications Zwie Amitai and Nusra Lodhi In many digital systems, high-speed transfers of data or instruc­ tions take place between sources and destinations that have different data rates. In other cases, the source and destination

Contextual Info: ASR-Soft Installation Installation on Windows Vista and Windows 7: 1 Insert the ASR-soft CD into the CD-ROM drive of your computer/laptop. The 2 When prompted for the destination directory as shown below, user can either installation wizard starts automatically and a Welcome screen appears, as

MELPS-740

Contextual Info: MITSUBISHI MICROCOMPUTERS SERIES M ELPS 740 ADDRESSING MODES SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ADDRESSING MODES contents or a com bination of both should be used to specify T h e series M E L P S 740 has 17 addressing m odes and an the m em ory or jum p destination. B ased on these 3 m ethods,

GTO Driver

Abstract: weak current AN10138
Contextual Info: National Semiconductor Application Note 1173 Milt Schwartz September 2000 INTRODUCTION The high data rates in today’s systems require extremely low skew clock distribution at a destination on a backplane logic card. Many systems also require a local clock to be distributed across a backplane. Therefore, creating a local distribution of clock signals with low-skew as well as providing a

AN-1173

Abstract: AN-905 DS92CK16
Contextual Info: National Semiconductor Application Note 1173 Milt Schwartz January 2002 INTRODUCTION The high data rates in today’s systems require extremely low skew clock distribution at a destination on a backplane logic card. Many systems also require a local clock to be distributed across a backplane. Therefore, creating a local distribution of clock signals with low-skew as well as providing a

Contextual Info: High-Speed CMOS 1 k x 64, 2k x 64 Content-Addressable Memory QCAM Q u a l it y Associative Processor S e m ic o n d u c t o r , I n c QS761480 QS762470 FEATURES DESCRIPTION • • • • The QS761480 and QS762470 is a family of 1k and 2k x 64-bit CAMs (content-addressable memories).

0309H

Contextual Info: Q u a l it y S e m ic o n d u c t o r , I n c High-Speed CMOS 1 k x 64, 2k x 64 Content-Addressable Memory QCAM Associative Processor . QS761480 QS762470 FEATURES DESCRIPTION • • • • The QS761480 and QS762470 is a family of 1k and 2k x 64-bit CAMs (content-addressable memories).

1523AN4

Abstract: ics1523
Contextual Info: Integrated Circuit Systems, Inc. Document Type: ICS1523 Application Note Document Stage: Release Designing a Custom PECL Interface for the ICS1523 1. Introduction This application note explains how to specify the pseudo emitter-coupled logic PECL interface when

inverter sla 1003

Abstract: sla 1003 MCD506 I2C-bus specification 3 2015 static ram microcontroller application PIR CONTROLLER sda 2023 P90CE201 P90CE201AEB MCD512
Contextual Info: INTEGRATED CIRCUITS DATA SHEET P90CE201 16-bit microcontroller Product specification File under Integrated Circuits, IC21 August 1993 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 CONTENTS 1 FEATURES 10 8-BIT GENERAL PORT 2 GENERAL DESCRIPTION

Contextual Info: ß S e m ic o n d u c to r, In c . High-Speed 3.3V CMOS qs74lcx2hsoi 9-Bit x 4 Ports Multiple Bus Exchange INF0ARDMVAA^ With BUS Hold, Output ReSIStOr and Synchronous/Asynchronous Controls FEATURES/BENEFITS DESCRIPTION • 5V-tolerant inputs and outputs • 25Q series resistor for low switching noise

Contextual Info: Quality S e m ico n d u cto r,In c QuickSwitch Products QS3B491 High-Speed C M O S qs 3 b249i Clocked 4 Port xA 9-Bit 9 DIL wlUl/KCU 4 r u i l advance INFORMATION CrossbarSwitch FEATURES/BENEFITS DESCRIPTION • The QS3B491 and QS3B2491 are high speed

Contextual Info: Preliminary Data Sheet S E M IC O N D U C T O R S APPLICATION BENEFITS DISTINCTIVE CHARACTERISTICS The 4096 x 64 bit LANCAM facilitates numerous operations: > New speed grade allows processing of both DA and SA within 560 ns, equivalent to 111, 10 Base-T or 11,100 Base-T Ethernet ports

MICROPROCESSOR 68000

Abstract: scn68000 SF4 357 signetics 68000 32bu 48DIP a231 ax hen no berh signetics 1016 16X16
Contextual Info: S i g n e t ic s 68000 16-/32-Bit Microprocessor Product Specification Military Customer Specific Products DESCRIPTION The 68000 is the first implementation of the 6800016/32 bit microprocessor archi­ tecture. The 68000 has a 16-bit data bus and 24-bit address bus, w hilethefull archi­

ICS1562A

Abstract: ICS1572 1572AN1 FR4 epoxy dielectric constant 4.6
Contextual Info: Integrated Circuit Systems, Inc. ICS1572 Document Type: Application Note Document Stage: Release Output Considerations for the ICS1572 1 Introduction The output considerations discussed in this application note apply to both the ICS1562A and the ICS1572. This application note includes a formula for calculating the trace width w that is needed to achieve the

3DA18

Abstract: AOXA scn680 SCN68000 SCN68000C6A68 SCN68000C6I64 SCN68000C6N64 SCN68000C8I64 SCN68000CAI64 SCN68000CAN64
Contextual Info: Mullard U Originally published by Signetics FEBRUARY 1985 SCN68000 16-Bit Microprocessor Product Specification DESCRIPTION PIN CONFIGURATION The SCN68000 is the first in a family of a d v a n c e d m ic ro p ro c e s s o rs fro m Signetics. Utilizing VLSI technology, the

Contextual Info: S G S -T H O M S O N Q œ[llL[iCTffi[i 0©i STLC5460 LINE CARD INTERFACE CONTROLLER • BOARD CONTROLLER FOR UP TO 16 ISDN LINES OR 16 VOICE SUBSCRIBERS. ■ TWO SERIAL INTERFACES : -PCM Four bidirectional multiplexes -GCI One or two at 2 Mb/s. ■ NON BLOCKING SWITCH FOR 128 CHAN­

Tuner sharp QPSK

Abstract: BS2S7VZ7A03 bs2s7vz BS2S7VZ6A02 dvb-t2 tuner VA3D5JZ714 tuner sharp
Contextual Info: RF • Digital DIGITAL DBS FRONT-END UNITS DBS Front-End Units ♦ Features 1 Equipped with a high-performance direct conversion IC. Reliability is improved by reducing power consumption and component counts. (2) Wide-band reception design also covering CS broadcast band. [Reception frequency: 950 to 2 150 MHz]

Contextual Info: Advance Information Draft T O ft MU9C1485A/L W idePort LANCAMs D IST IN C T IV E C H A R A C T E R IS T IC S G E N E R A L D E S C R IP T IO N The MU9C1485A and MU9C1485L WidePort LANCAMs are 1048 x 64-bit content-addressable memories CAMs , featuring a 32-bit wide interface. This interface doubles the