DC/DECA D16 Search Results

500-187

Abstract: CS5323 CS5322 CS5322-BL CS5322-KL LT1021 576716 dc/deca d16
Contextual Info: CS5322 CS5323 Semiconductor Corporation 24-Bit Variable Bandwidth A/D Converter Features General Description • • Dynamic Range The CS5323 analog modulator and the CS5322 digital filter function together as a unique high resolution A/D converter intended for geophysical and other applicat io ns w hi c h r e qu ir e hi gh dy namic r ange. The

CS5323

Abstract: CS5322 CS5322-BL CS5322-KL
Contextual Info: CS5322 CS5323 24-Bit Variable Bandwidth A/D Converter Features Description l Monolithic The CS5323 analog modulator and the CS5322 digital filter function together as a unique high resolution A/D converter intended for geophysical and other applications which require high dynamic range. The

CS5323

Abstract: CS5322 CS5322-BL CS5322-KL fft algorithm
Contextual Info: A DIVISION OF * CIRRUS LOGIC' 24-Bit Variable Bandwidth A/D Converter Features Description • M onolithic CM OS A/D Converter • Dynamic Range - 130 dB @ 25 Hz Bandwidth - 120 dB @411 Hz Bandwidth The CS5323 analog modulator and the CS5322 digital filter function together as a unique high resolution A/D

Contextual Info: a DSP Microcomputer ADSP-2171/ADSP-2172/ADSP-2173 FEATURES 30 ns Instruction Cycle Time 33 M IPS from 16.67 M Hz Crystal at 5.0 V 50 ns Instruction Cycle Time (20 M IPS) from 10 M Hz Crystal at 3.3 V ADSP-2100 Family Code & Function Compatible w ith New Instruction Set Enhancements for Bit M anipulation Instructions, M ultiplication Instructions, Biased

Contextual Info: a Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FU NCTIONAL B LOCK D IAGRAM SUM M ARY 16-Bit Fixed-Point DSP M icroprocessors w ith On-Chip M emory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, M ultiplier/

Programmable Timer Counter

Abstract: 0004H HT9480
Contextual Info: HT9480 Pager Controller Features • • • • • • • • • • • • • • • Operating voltage: 2.2V~3.5V Low power crystal oscillator control – 512, 1200, or 2400 bps data rate operation Decodes CCIR Radio-paging Code No.1 POCSAG Code

SP2111

Abstract: PMS 102 0050 PH ys 2103
Contextual Info: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUM M ARY 16-Bit Fixed-Point DSP M icroprocessors w ith On-Chip M emory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, M ultiplier/

"Pager receiver"

Abstract: Code A08 RF Semiconductor POCSAG HT9280 HT9380 CCIR Radiopaging Code NO.1 spf301
Contextual Info: HT9280/HT9380 Pager Controller Features • • • • • • • • • • • • • Operating voltage: 2.2V~3.5V Low power crystal oscillator control – 512, 1200 or 2400 bps data rate 8Kx16 program ROM 320×8 data RAM 35×4 LCD display 7 input lines, and 10 bidirectional I/O lines

Code A08 RF Semiconductor

Abstract: CCIR Radiopaging Code NO.1 HT92801 HT93801
Contextual Info: HT92801/HT93801 OTP Pager Controller Features • • • • • • • • • • • • • • Operating voltage: 2.6V~3.5V Low power crystal oscillator control – 512, 1200 or 2400 bps data rate Decodes CCIR Radio-paging Code No.1 POCSAG Code 2-bit or 4-bit burst error correction

Contextual Info: a FEATURES PERFORM ANCE 25 ns Instruction Cycle Time from 20 M Hz Crystal @ 5.0 Volts 40 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Sw itch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

Code A08 RF Semiconductor

Abstract: f10 60s POCSAG Receiver 0004H HT94801
Contextual Info: HT94801 OTP Pager Controller Features • • • • • • • • • • • • • • • • Operating voltage: 2.6V~3.5V Low power crystal oscillator control – 512, 1200 or 2400 bps data rate Decodes CCIR Radio-paging Code No.1 POCSAG Code 2-bit random and optional 4-bit burst error

d 998

Abstract: LFX1200B-02F900I
Contextual Info: ispXPGA Family TM July 2002 Advance Data Sheet • Eight sysCLOCK Phase Locked Loops PLLs for Clock Management Features ■ Non-volatile, Infinitely Reconfigurable • • • • • • Instant-on - Powers up in microseconds via on-chip E2CMOS based memory

S2MC

Abstract: D-16 D-10 D-12 K310S 1AM7 MB74
Contextual Info: LXD916/917 Reference Design Schematics Reference Design Schematics Reference Design Schematic, Sheet 1:Top Level Schematic S E CONDA RY A UI 2 DO+ A UI 2 DOAUI 2 DI + AUI 2 DI AUI 2 CI + AUI 2 CI A U I MO D E CL K 2 0 A A R B OU T MS T O U T SE RDA T SE RCL K

EM78F541NASO16A

Contextual Info: EM78F541N 8-Bit Microcontroller Product Specification DOC. VERSION 0.9 ELAN MICROELECTRONICS CORP. September 2009 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo

8x8 DOT MATRIX 12 pin configurations

Abstract: COUNTER MODULO 504 COUNTER MODULO 503 mPC 514 MAB8048 PC10 PCF84C230 TF 2309 14-segment display map 8E1Y
Contextual Info: DEVELOPMENT DATA 34E e This data sheet contains advance information and specifications are subject to change without notice. 711Qñ2b 00H 473 7 H PCF84C230 PHILIPS INTERNATIONAL T - M R - f l- o S SINGLE-CHIP 8-BIT MICROCONTROLLER WITH LCD DRIVER GENERAL DESCRIPTION

5xxN

Contextual Info: EM78F541N 8-Bit Microcontroller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. January 2010 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo

a4 81p

Abstract: gsr 600
Contextual Info: ispXPGA Family TM March 2003 Preliminary Data Sheet • Non-volatile, Infinitely Reconfigurable ■ Eight sysCLOCK Phase Locked Loops PLLs for Clock Management • Instant-on - Powers up in microseconds via on-chip E2CMOS based memory • No external configuration memory

118p

Abstract: 31n w6 resistor 85n a4 81p mux 232n
Contextual Info: ispXPGA Family TM May 2003 Preliminary Data Sheet • Non-volatile, Infinitely Reconfigurable ■ Eight sysCLOCK Phase Locked Loops PLLs for Clock Management • Instant-on - Powers up in microseconds via on-chip E2CMOS based memory • No external configuration memory

THERMAL Fuse m20 tf 115 c

Abstract: mux 232n 144n 129P 244n
Contextual Info: ispXPGA Family TM March 2003 Preliminary Data Sheet • Non-volatile, Infinitely Reconfigurable ■ Eight sysCLOCK Phase Locked Loops PLLs for Clock Management • Instant-on - Powers up in microseconds via on-chip E2CMOS based memory • No external configuration memory

0004H

Abstract: HT9480
Contextual Info: HT9480 Pager Controller Features • · · · · · · · · · · · Operating voltage: 2.4V~3.3V Low power crystal oscillator control – 512, 1200, or 2400 bps data rate operation Decodes CCIR Radio-paging Code No.1 POCSAG Code 2-bit random and optional 4-bit burst error

Contextual Info: EM78F641N 8-Bit Microcontroller Product Specification DOC. VERSION 2.1 ELAN MICROELECTRONICS CORP. January 2010 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo

EM78F641NASO16AJ

Contextual Info: EM78F641N 8-Bit Microcontroller Product Specification DOC. VERSION 2.0 ELAN MICROELECTRONICS CORP. September 2009 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo

0004H

Abstract: HT9480
Contextual Info: HT9480 8-Bit Numerical Pager Controller MCU Features • Operating voltage: 2.4V~3.3V · 7 input lines and 10 bidirectional I/O lines · Low power crystal oscillator control · 8-bit programmable timer for RTC interrupt - 512, 1200, or 2400 bps data rate operation

CCIR Radiopaging Code NO.1

Contextual Info: HT9480 Pager Controller Features • · · · · · · · · · · · Operating voltage: 2.2V~3.5V Low power crystal oscillator control – 512, 1200, or 2400 bps data rate operation Decodes CCIR Radio-paging Code No.1 POCSAG Code 2-bit random and optional 4-bit burst error