DATA TABLE ACCESS MODULE Search Results

Contextual Info: FM28V100 1-Mbit 128 K x 8 F-RAM Memory Features • 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table)

LD33

Abstract: multiplier accumulator MAC code VHDL a016 b24 b03 MULT18X18 SRIB16
Contextual Info: LatticeECP2/M sysDSP Usage Guide June 2010 Technical Note TN1107 Introduction This technical note discusses how to access the features of the LatticeECP2 and LatticeECP2M™ sysDSP™ Digital Signal Processing Block described in the LatticeECP2/M Family Data Sheet. Designs targeting the sysDSP Block can offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an

Contextual Info: 19-6259; Rev 1; 8/12 DS1886 SFP and PON ONU Controller with Digital LDD Interface General Description The DS1886 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality for GPON/EPON and 10G PON ONU applications. The combination of the DS1886 with the MAX3710

Contextual Info: DS1876 SFP Controller with Dual LDD Interface General Description The DS1876 controls and monitors all functions for dual transmitter modules. The memory map is based on SFF-8472. The DS1876 supports APC and modulation control and eye safety functionality for two laser

Contextual Info: 19-5153; Rev 0; 2/10 SFP Controller with Dual LDD Interface The DS1876 controls and monitors all functions for dual transmitter modules. The memory map is based on SFF-8472. The DS1876 supports APC and modulation control and eye safety functionality for two laser

DPRAM

Abstract: CY7C028V DSP56300 MSC8101 SC140 pgpl5
Contextual Info: Order Number AN2146/D: Rev. 2 6/26/2001 MOTOROLA Semiconductor Products Sector Application Note Interfacing the MSC8101 UPM to an External Dual-Port SRAM Iantha E. Scheiwe The MSC8101 is a powerful DSP that integrates the StarCore DSP core, a Communications Processor Module CPM for

Contextual Info: Standard Products UT8ER1M32 32Megabit SRAM MCM UT8ER2M32 64Megabit SRAM MCM UT8ER4M32 128Megabit SRAM MCM Data Sheet January, 2013 www.aeroflex.com/memories INTRODUCTION The UT8ER1M32, UT8ER2M32, and UT8ER4M32 are high performance CMOS static RAM multichip modules MCMs

Contextual Info: Standard Products ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module www.aeroflex.com/Avionics March 18, 2005 FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ Six 6 Low Power 1M x 16 Synchronous Dynamic Random Access Memory Chips in one MCM

Contextual Info: Standard Products ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module www.aeroflex.com/Avionics May 30, 2006 FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ Six 6 low power 1M x 16 synchronous dynamic random access memory chips in one MCM

DQ85

Contextual Info: ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM I I I I I I Multichip Module - H eatures 6 Low Power Texas Instruments 1M X 16 Synchronous Dynamic Random Access Memory Chips in one MCM User Configureable as "2" Independent 512K X 48 X 2 Banks High-Speed, Low-Noise, Low-Voltage TTL LVTTL

Contextual Info: Standard Products UT9Q512K32E 16 Megabit RadTolerant SRAM MCM Data Sheet June 28, 2011 INTRODUCTION The UT9Q512K32E RadTol product is a high-performance 2M byte 16Mbit CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a

TBD CABLE

Abstract: taclane redcom Cisco 3725 lan rj45 color code diagram EIA-470B CA9079 RS-232 trackball db25m pinout DB50 connector
Contextual Info: TDC Theater Deployable Communications Baseline Requirements Document Initial Communications Element - Voice/NIPRNET Module v2 Nov 2003 ESC/NI4T 5 Eglin Street Hanscom AFB, MA 01731 Approved for public release; distribution is unlimited. FA8726-04-R-0002

tmm-104-03-t-d

Abstract: TFM-140-32-S-D-LC 1G04 SN74CBT3257 TMS320 TMS320C5000 TMS320C5402 TMS320C6000 TMS320C6711 HEADER 2MM 20PIN
Contextual Info: User's Guide SLAU104C – May 2004 – Revised March 2009 5–6K Interface Board The 5-6K Interface Board provides a complete system development platform using evaluation modules from the Data Acquisition Products Group. This board passes signals from TMS320C5000 and

Static Random Access Memory SRAM

Abstract: F848 f840 F844 F84A F852 MC68F375 F85A
Contextual Info: SECTION 11 STATIC RANDOM ACCESS MEMORY SRAM 11.1 Introduction This SRAM module is a fast access (two clocks) general purpose 8K (8,192 bytes) static RAM (SRAM) for the MCU and is accessed via the IMB3. In addition there is 2K (configured as four blocks of 512 bytes each) of patch static RAM. These modules are

UM0470

Abstract: STM8 CPU programming manual SWIM STM8 USB send BK2R22 PM0047 STM8 SWIM communication protocol and debug module UM0470 STM8 programming manual PC15 SP15
Contextual Info: UM0470 User manual STM8 SWIM communication protocol and debug module Introduction This manual has been written for developers who need to build programming, testing or debugging tools for the STM8 microcontroller family. It explains the debug architecture of the

F844

Abstract: Static Random Access Memory SRAM F848 power transistor array F840 F84A F852 MC68377 memory sram
Contextual Info: SECTION 12 STATIC RANDOM ACCESS MEMORY SRAM 12.1 Introduction This SRAM module is a fast access (two clocks) general purpose 8 Kbytes (8,192 bytes) static RAM (SRAM) for the MCU and is accessed via the IMB3. In addition there is 2 Kbytes (configured as four blocks of 512 bytes each) of patch static RAM. These

CPU H8/532

Abstract: H8/520 H8/532 H8/500 Programming Manual HD6435328F p349 p71 0107 LB 124 d Hitachi DSA0044 HS538ESC01H
Contextual Info: H8/532 Hardware Manual Preface The H8/532 is a high-performance single-chip Hitachi-original microcomputer, featuring a highspeed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules. The H8/532 is an ideal microcontroller for a wide variety of medium-scale devices, including both

SAK-C167CR-LM

Abstract: SAF-C167CR-LM ba C167CR SAB-C167CR-LM injection cpu application C166 C167 C167CR-LM SAF-C167CR-LM
Contextual Info: Microcomputer Components Technical Support Group Munich HL MCB AT 1 Errata Sheet February 2, 1996 / Release 1.1 Device : Stepping Code / Marking : SAB-C167CR-LM, SAF-C167CR-LM, SAK-C167CR-LM ES-BA, BA The C167CR is a version of the C167 with on-chip CAN module, 2 Kbyte XRAM

Contextual Info: TM2EP640PN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP720JN, TM4EP72DPN, TM4EP72DJN EXTENDED-DATA-OUT DYNAMIC RAM MODULES Organization - TM2EP64DxN . . . 2097152 x 64 Bits - TM2EP72DxN . . . 2097152 x 72 Bits - TM4EP64DxN . . . 4194304 x 64 Bits

Contextual Info: 32MB, 64MB, 128MB x64, SR 168-PIN SDRAM UDIMM SYNCHRONOUS DRAM MODULE MT4LSDT464A – 32MB MT4LSDT864A(I) – 64MB MT4LSDT1664A(I) – 128MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features • •

Contextual Info: TDA7546 Multichip module for TMC tuner applications Features • High-performance FM receiver ■ SW-Controlled world tuning ■ Variable bandwidth IF filter ISS, intelligent selectivity system ■ Programmable quality detectors ■ High-speed PLL for RDS operation

IAI5

Contextual Info: bq4822Y U N IT R O O E - RTC Module with 8Kx8 NVSRAM Features General Description > Integrated SRAM, real-time clock, CPU supervisor, crystal, power-fail circuit, and battery The bq4822Y RTC Module is a non­ volatile 65,536-bit SRAM organized as 8192 words by 8 bits with an in­

BD-962

Contextual Info: bq4852Y U IM IT R O D E RTC Module with 512Kx8 NVSRAM Features General Description ► I n te g r a te d SRAM, re a l-tim e clock, CPU supervisor, crystal, pow er-fail control circuit, and battery The bq4852Y RTC Module is a non­ volatile 4,194,304-bit SRAM organ­

RTD 1055

Abstract: PAMUX E1017-11 1055 IN1822
Contextual Info: BRAINS SNAP ANALOG AND DIGITAL DATA SHEET Form 1055-071121 page 1/9 Part Number Description SNAP-B6 High Speed Analog/Digital Pamux Brain Description The SNAP-B6 is a high-speed, addressable brain that can remotely control a mix of both analog and digital I/O modules,