DATA SHEET CMOS PIN CONFIGURATION LAYOUT Search Results

M02046-14

Abstract: MC2046
Contextual Info: Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. M02046-14/-24 3.3V Limiting Amplifier for Applications to 1.25 Gbps The M02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and footprint as the MC2046-2 refer to 02046-APP-004-X where X is the revision which will change if the application note is

Contextual Info: FEATURES ±15 kV ESD protection on output pins 400 Mbps 200 MHz switching rates Flow through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 V power supply ±310 mV differential signaling

Contextual Info: FEATURES ±15 kV ESD protection on output pins 400 Mbps 200 MHz switching rates Flow through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 V power supply ±310 mV differential signaling

A0145-L-006-3

Contextual Info: FUNCTIONAL BLOCK DIAGRAM REF_SEL MCLK_x Rx AD9574 OUT0_P OUT0_N OUT1_P Rx OUT1_N REF_ACT REF_SW REF_FLO REF_FHI REFMON PPRx x1/×2 ×1/×2 PFD/ CP LF LD LF PPR CONTROL VCO OUT2_P OUT2_N OUT3_P OUT3_N OUT4_P OUT4_N OUT5_P OUT5_N OUT6_P OUT6_N 07501-001 REF0_P

cell phone camera module

Abstract: 14 pin cmos IMAGE SENSOR 3.2 Megapixel QXGA camera module "compact camera module" CMOS QXGA vertical sync CMOS digital image sensor with global shutter cmos image sensor Hsync Vsync ap CMOS Bayer CMOS digital image sensor
Contextual Info: ADVANCE INFORMATION - CONFIDENTIAL The Leader in CMOS Image Sensors ICM320T 3.2 Megapixel QXGA Digital Color CMOS Image Sensor Preliminary Data Sheet V1.0 General Description Applications The ICM320T is a high resolution, low power, small form factor device 3.2Megapixel digital color CMOS

Contextual Info: 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9650 Data Sheet FEATURES APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers

HC9S08JM

Contextual Info: Data Sheet May 2012 DS31408 Demo Kit General Description The DS31408DK is an easy-to-use evaluation kit for the DS31408 timing IC. A surface-mounted DS31408 and careful layout provide maximum signal integrity. An onboard low-phase-noise stratum 3 quality oscillator is

Contextual Info: FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: Data Sheet May 2012 DS3106DK Demo Kit Evaluates: DS3106 Timing IC General Description The DS3106DK is an easy-to-use demo and evaluation kit for the DS3106 line card timing IC. A surface-mounted DS3106 and careful layout provide maximum signal integrity. An on-board 8051compatible microcontroller and included software

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

High Frequency Device Data Book

Abstract: 5 pin relay data sheet scr drive circuit diagram ac voltage regulator using SCR circuit diagram High power SCR scr power supplies EPC1441
Contextual Info: Operating Requirements December 1999, ver. 9.02 for Altera Devices Data Sheet 1 Introduction Altera® devices combine unique programmable logic architectures with advanced CMOS processes to provide exceptional performance and reliability. To maintain the highest possible performance and reliability of

eprom UV eraser

Abstract: EPC1441
Contextual Info: Operating Requirements December 1999, ver. 9.02 for Altera Devices Data Sheet 1 Introduction Altera® devices combine unique programmable logic architectures with advanced CMOS processes to provide exceptional performance and reliability. To maintain the highest possible performance and reliability of

C5447

Abstract: SANYO DA11 sanyo R51 C53-C58 4816p-001-220 DAC5687 GRM42X5R106K10 C84-C86
Contextual Info: DAC5687 EVM User's Guide March 2007 Wireless Infrastructure Products SLWU017B 2 SLWU017B – APRIL 2005 – Revised March 2007 Submit Documentation Feedback Contents 1 Overview . 5

Sine Wave Generator stp 2740

Contextual Info: FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver MPC9315 NRND DATASHEET NRND – Not Recommend for New Designs The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The

Contextual Info: Data Sheet May 2012 DS31415 Demo Kit General Description The DS31415DK is an easy-to-use evaluation kit for the DS31415 timing IC. A surface-mounted DS31415 and careful layout provide maximum signal integrity. An onboard low-phase-noise TCXO is provided for device

A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

A115-A

Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
Contextual Info: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout

Contextual Info: 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver ICS843N001I NRND DATASHEET NRND – Not Recommend for New Designs The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to

Contextual Info: 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9266 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 77.6 dBFS at 9.7 MHz input 71.1 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input

Contextual Info: Data Sheet May 2012 DS3104DK Demo Kit Evaluates: DS3104 Timing IC General Description The DS3104DK is an easy-to-use demo and evaluation kit for the DS3104-SE line card timing IC. A surface-mounted DS3104-SE and careful layout provide maximum signal integrity. An on-board 8051compatible microcontroller and included software

Contextual Info: Data Sheet May 2012 DS3102DK Demo Kit Evaluates: DS3102 Timing IC General Description The DS3102DK is an easy-to-use demo and evaluation kit for the DS3102 line card timing IC. A surface-mounted DS3102 and careful layout provide maximum signal integrity. An on-board 8051compatible microcontroller and included software

Contextual Info: Data Sheet May 2012 DS31406 Demo Kit General Description The DS31406DK is an easy-to-use evaluation kit for the DS31406 timing IC. A surface-mounted DS31406 and careful layout provide maximum signal integrity. An onboard low-phase-noise stratum 3 quality oscillator is

Contextual Info: Data Sheet May 2012 DS3105DK Demo Kit Evaluates: DS3102 TimingIC General Description The DS3105DK is an easy-to-use demo and evaluation kit for the DS3105 line card timing IC. A surface-mounted DS3105 and careful layout provide maximum signal integrity. An on-board 8051compatible microcontroller and included software