DATA EQUALIZATION SYSTEM Search Results

3FEh-40Ch

Abstract: MS-026 PCM1744 S-PQFP-G48 TAS3001 TAS3002 TAS3002PFB TAS3002PFBG4 TLV2362
Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

CAT5E Pinout

Abstract: WBC1-1TLB eqco400t EQCO400T5 Eqcologic 1394B-2002 IEEE1394-2008 eqco WBC1-1TL MO-220
Contextual Info: EqcoLogic NV Engineering Information Open your Eyes EQCO400T - UTP Cable Equalizer for IEEE 1394b 1.1 Features • •        Patented Eqcologic adaptive equalization technology Multi-Rate Adaptive Equalization Supports IEEE 1394b - S400, S200 and S100 data rates

Contextual Info: SY56020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020R is a fully-differential, low-voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020R can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps.

Contextual Info: SY56020XR Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020XR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020XR can process clock signals as fast as 4.5GHz or data patterns up to

SY56020RMG

Abstract: 10-0108 R020
Contextual Info: SY56020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020R can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps.

Contextual Info: DS34RT5110 DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis Literature Number: SNLS310F DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output DeEmphasis General Description Features The DS34RT5110 is a 10.2 Gbps 3 x 3.4 Gbps high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS ) data channels and a

LLP-36

Contextual Info: DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit PreEmphasis and Receive Equalization General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output Pre-emphasis that enable data communication in FR4 backplane up

Contextual Info: DS42MB100 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit DeEmphasis and Receive Equalization General Description Features The DS42MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output de-emphasis that enable data communication in FR4 backplane up

Contextual Info: Document Number: DSP56366 Rev. 3.1, 1/2007 Freescale Semiconductor Data Sheet: Technical Data DSP56366 24-Bit Audio Digital Signal Processor 1 Overview The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization,

DS42MB100

Abstract: DS42MB100TSQ
Contextual Info: DS42MB100 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit PreEmphasis and Receive Equalization General Description Features The DS42MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output pre-emphasis that enable data communication in FR4 backplane up

obsai

Contextual Info: DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit DeEmphasis and Receive Equalization General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output de-emphasis that enable data communication in FR4 backplane up

Contextual Info: DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer

GS9025

Abstract: GS9025A GS9025ACQM GS9025ACTM GS9028
Contextual Info: * 1/,1; , GS9025A Serial Digital Receiver DATA SHEET DESCRIPTION • SMPTE 259M compliant The GS9025A provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS9025A receives either single-ended or

EB9024

Abstract: GS9024 GS9024-CKB GS9024-CTB GS9028
Contextual Info: GENLINX II GS9024 Automatic Cable Equalizer DATA SHEET DESCRIPTION • automatic cable equalization The GS9024 is a high performance automatic cable equalizer designed for serial digital data rates from 143Mb/s to 540Mb/s. The GS9024 receives either single-ended or

Contextual Info: DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer

GU13

Contextual Info: GENLINX II GS9024 Automatic Cable Equalizer DATA SHEET DESCRIPTION • automatic cable equalization The GS9024 is a high performance automatic cable equalizer designed for serial digital data rates from 30Mb/s to 622Mb/s. The GS9024 receives either single-ended or

Contextual Info: July 2006 DS25MB200 Dual 2.5 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS25MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 2.5 Gb/s. Each input stage has a fixed equalizer

PRBS7

Abstract: DS25MB200 DS25MB200TSQ
Contextual Info: March 2006 DS25MB200 Dual 2.5 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis General Description Features The DS25MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 2.5 Gb/s. Each input stage has a fixed equalizer

T7290A

Abstract: T7689
Contextual Info: Data Sheet May 1998 T7689 5.0 V T1 Quad Line Interface Features • Four fully integrated T1 line interfaces ■ Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions ■ Ultralow power consumption ■ Robust operation for increased system margin

T7290A

Abstract: T7690 T7693 2483rd
Contextual Info: systemsAdLib ~rl " ere OCR Evaluation Data Sheet July 2002 T7690 5.0 V T1/E1 Quad Line Interface T7693 3.3 V T1/E1 Quad Line Interface 1 Features 3 Overview . Four fully integrated T1/E1 line interfaces . Includes all driver, receiver, equalization, clock recovery,

89H48H12

Abstract: 89H48H12G3
Contextual Info: 48-Lane 12-Port PCIe Gen3 System Interconnect Switch 89HPES48H12G3 Data Sheet ® Device Overview – Autonomous and software managed link width and speed control – Per lane SerDes configuration • Full back channel equalization support • Rx, 5 tap DFE

T7290A

Contextual Info: Data Sheet May 1998 T7688 5.0 V E1/CEPT Quad Line Interface Features • Four fully integrated E1 line interfaces ■ Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions ■ Ultralow power consumption ■ Robust operation for increased system margin

CM23

Abstract: GS7025 GS9020 GS9024 GS9025A GS9028
Contextual Info: GS7025 PRO-LINX Serial Digital Receiver Key Features Description • SMPTE 259M-C compliant 270Mb/s • Automatic cable equalization (typically greater than 350m of high-quality cable) • Serial data outputs muted and serial clock remains active when input data is lost

AD8153

Abstract: AD8159
Contextual Info: 3.2 Gbps Single Buffered Switch AD8153 Preliminary Technical Data FEATURES Single lane 2:1 mux/1:2 demux 3.2 Gbps to DC data rates Compensates over 40 inches of FR4 at 3.2 Gbps through Two levels of input equalization, or Four levels of output pre-emphasis