DATA EQUALIZATION SYSTEM Search Results

Contextual Info: Agilent Technologies N5461A Serial Data Equalization Software for Infiniium Series Oscilloscopes Data Sheet Significantly reduce receiver errors by opening even tightly shut eyes through equalization emulation The Agilent Technologies serial data equalization software for Infiniium

DSO9000A

Abstract: E2688A N5384A 5989-7819EN DSO90000A DATA EQUALIZATION SYSTEM
Contextual Info: Agilent Technologies N5461A Serial Data Equalization Software for Infiniium 90000 and 9000 Series Oscilloscopes Data Sheet Significantly reduce receiver errors by opening even tightly shut eyes through equalization emulation The Agilent Technologies serial data

AN643

Abstract: 75180 APP643 MAX3291 MAX3292
Contextual Info: Maxim > App Notes > INTERFACE CIRCUITS Keywords: RS-485, rs485, EIA/TIA-485, data transceiver, pre-emphasis, pre-equalization, equalization Jan 22, 2001 APPLICATION NOTE 643 Pre-Emphasis Improves RS-485 Communications Abstract: Intersymbol interference in RS-485 data transmission systems is discussed, with emphasis on

TSB89

Abstract: Commscope operational amplifier discrete schematic RS-485 abstract SLLA104 LTC1485 MAX485 SN65HVD21 SN65HVD23 THS4140
Contextual Info: Application Report SLLA169 – August 2004 Use Receiver Equalization To Extend RS-485 Data Communications Clark Kinnaird High Performance Analog/Interface Products ABSTRACT Systems designers can use receiver equalization to extend their RS-485 data transmission applications in terms of longer cable distances or higher signaling rates. This

Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

3FEh-40Ch

Abstract: MS-026 PCM1744 S-PQFP-G48 TAS3001 TAS3002 TAS3002PFB TAS3002PFBG4 TLV2362
Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

638h-646h

Contextual Info: TAS3002 Digital Audio Processor With Codec Data Manual 2001 Digital Audio: Digital Speakers SLAS307B 1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM DC to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at 10.3125 Gbps Compensates 15 inches of FR408 at 11.3 Gbps 6-tap programmable transmit feedforward equalization FFE

CAT5E Pinout

Abstract: WBC1-1TLB eqco400t EQCO400T5 Eqcologic 1394B-2002 IEEE1394-2008 eqco WBC1-1TL MO-220
Contextual Info: EqcoLogic NV Engineering Information Open your Eyes EQCO400T - UTP Cable Equalizer for IEEE 1394b 1.1 Features • •        Patented Eqcologic adaptive equalization technology Multi-Rate Adaptive Equalization Supports IEEE 1394b - S400, S200 and S100 data rates

R017

Contextual Info: SY56017R Low Voltage 1.2V/1.8V/2.5V CML 2:1 MUX 6.4Gbps with Equalization General Description The SY56017R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 2:1 MUX with input equalization. The SY56017R can process clock signals as fast as 4.5 GHz or data patterns up to 6.4Gbps.

Contextual Info: SY56020XR Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020XR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020XR can process clock signals as fast as 4.5GHz or data patterns up to

Contextual Info: SY56020XR Low Voltage 1.2V/1.8V/2.5V CML 1:4 FANOUT BUFFER 6.4GBPS with EQUALIZATION . General Description The SY56020XR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020XR can process clock signals as fast as 4.5GHz or data patterns up to

Contextual Info: SY56020XR Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020XR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020XR can process clock signals as fast as 4.5GHz or data patterns up to

SY56020RMG

Abstract: 10-0108 R020
Contextual Info: SY56020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020R can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps.

QFN-16

Abstract: R020
Contextual Info: SY56020R Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer 6.4Gbps with Equalization General Description The SY56020R is a fully-differential, low-voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with input equalization. The SY56020R can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps.

SAA7323

Abstract: tda1316 TDA1317 SAA2002 SAA2022 SAA2032 SAA2032GP SAA7360 TDA1318 "Tape drive"
Contextual Info: INTEGRATED CIRCUITS DATA SHEET SAA2032 Digital equalization for the tape drive processing of the DCC system Product specification Supersedes data of February 1993 File under Integrated Circuits, Miscellaneous Philips Semiconductors February 1995 Philips Semiconductors

Contextual Info: DS34RT5110 DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis Literature Number: SNLS310F DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output DeEmphasis General Description Features The DS34RT5110 is a 10.2 Gbps 3 x 3.4 Gbps high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS ) data channels and a

Contextual Info: DS42MB100 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit PreEmphasis and Receive Equalization General Description Features The DS42MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output pre-emphasis that enable data communication in FR4 backplane up

LLP-36

Abstract: 9435k DS25MB100 DS25MB100TSQ
Contextual Info: DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit PreEmphasis and Receive Equalization General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output Pre-emphasis that enable data communication in FR4 backplane up

LLP-36

Contextual Info: DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit PreEmphasis and Receive Equalization General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output Pre-emphasis that enable data communication in FR4 backplane up

DS25MB100

Abstract: DS25MB100TSQ
Contextual Info: DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit DeEmphasis and Receive Equalization General Description Features The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy or cable driving applications. Signal conditioning features include input equalization and programmable output de-emphasis that enable data communication in FR4 backplane up