DALLAS LOGIC Search Results

Contextual Info: TPIC6E175 POWER LOGIC EEPROM-PROGRAMMABLE QUAD D-TYPE LATCH SLIS052 - NO VEM BER 1995 NE PACKAGE TOP VIEW Programmable-PWM Current Threshold Programmable-PWM Frequency Controlled by Internal or External Oscillator O S C /V E R [ 1 DRAIN1 [ 2 Integrated Output Recirculation Clamp

5 to 32 decoder

Contextual Info: TPIC6E585 POWER LOGIC EEPROM-PROGRAMMABLE 4-BIT SHIFT-REGISTER PWM DRIVER SLIS025 - SEPTEMBER 1995 • Programmable-PWM Current Threshold • Integrated Output Recirculation Clamp Diodes OSC/VER [ 1 DRAIN1 [ 2 SER IN/A0 [ 3 SRCLR/A1 [ 4 • Low rDS on . . . 1 Q T V P

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

Contextual Info: sse • d flui?a3 ODflbiflfl t SNS4HC4066, TLC4066I SILICQN-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH TEXAS INSTR LOGIC 02922, JANUARY 1988 High Degree of Linearity SN64HC4066 . . . J OR N PACKAGE T L C 40 66 I. . . D OR N PACKAG E • High On-Off Output Voltage Ratio

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

Contextual Info: TEXAS INSTR 0=^1723 oaaBü? 1 5SE D LOGIC SN54ALS131, SNB4AS131A, SN74ALS131, SN74AS131A 3-LINE TO 8-LINE DECODERSIDEMULTIPLEXERS WITH ADDRESS REGISTERS r-<U.-2('55 D 2 6 6 1 , A PRIL 1 9 8 2 - R E V IS E D M AY 1986 SN54ALS131, SN54AS131A . . . J PACKAGE

Contextual Info: SN54HC623, SN74HC623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS149A - DECEMBER 1982 - REVISED JANUARY 1996 Lock Bus-Latch Capability True Logic High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options include Plastic Small-Outline DW and Ceramic Flat

t742

Contextual Info: SN54F621, SN74F621 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS SDFS004B - D2932, MARCH 1987 - REVISED OCTOBER 1993 • Local Bus-Latch Capability • Noninverting Logic • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic

d2439

Abstract: p725
Contextual Info: MC3423 OVERVOLTAGE-SENSING CIRCUIT D2439, A P R IL 1978— RE V IS E D M A R C H 1988 * D OR P PACKAGE Separate Outputs for Crowbar and Logic Circuitry TOP VIEW Programmable Time Delay to Eliminate Noise Triggering TTL-Level Activation Isolated From Voltage-Sensing Inputs

74als666

Abstract: 74ALS667 2561a
Contextual Info: SN 5 4 A LS 6 6 6 , SN 5 4 A LS6 6 7 , SN 7 4 A LS 6 6 6 , S N 7 4 A LS 6 6 7 8 BIT D TYPE T R A N SP A R E N T R EAD-BACK LATCHES W ITH 3-STATE O U TPU TS D 2 8 5 5 , JUNE 1 9 8 4 - • 3-State l/O-Type Read-Back Inputs • Bus-Structured Pinout • Choice of True or Inverting Logic

Contextual Info: TIB82S167BM , TIB82S167BC 1 4 x 4 8 x 6 FIELD PROGRAM M ABLE LOGIC SEQUENCER WITH 3 STATE OUTPUTS OR PRESET D2896, JANUARY 198b-REVISED DECEMBER 1987 Programmable Asynchronous Preset or Output Control M SU FFIX . . . J T PACKAGE C SUFFIX . . . J T OR N T PACKAGE

74690

Abstract: 74692 8Q21
Contextual Info: TFyAi TNSTR LOGIC T EX A S I N S T R { L O G I C ! 1 1 91D 74690 D T-5£-0? D E | 0 ^ 1 7 2 3 DD74h1G 5 1 ~ SN 74 A S 18 2 3 9-BIT BUS INTER FA CE FLIP-FLUPS WITH 3-STATE OUTPUTS APRIL 1 9 8 7 NT PACKAGE Center V q c ar|d GND Configuration Provides Minimum Lead Inductance in High

18n8

Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic

LT10711

Contextual Info: LT1071, LT1071HV 2.5-A HIGH-EFFICIENCY SWITCHING REGULATORS D3344, JULY 19B 9-R E V IS E D A U G U S T 1991 Wide Supply-Voltage Range: LT1071HV . . . 3 V to 60 V LT1071 . . . 3 V to 40 V KC AND KV PACKAGE KV Package Used for Illustration (TOP VIEW) Low Quiescent Current. . . 6 mA Typ

CT 2048

Abstract: D8228
Contextual Info: SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L 2048 x 9,4096 x 9,8192 x 9,16384 x9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 Reads and Writes Can Be Asynchronous or Coincident Organization: - SN74ACT7203L - 2048 x 9

Contextual Info: TPS9103 POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A - JULY 1996 Charge Pump Provides Negative Gate Bias for Depletion-Mode GaAs Power Amplifiers GATE_BIAS □ = 10 VCC C1c i+ BATTJN BATTJN BATTJN PGP PG GND 2 3 4 5 6 7 8 9 10 135-mli High-Side Switch Controls Supply

74AC138

Abstract: TLV5633 TLV5633C TLV5633CDW TLV5633CPW TLV5633I TLV5633IDW TLV5633IPW intel MCS-51 microcontroller
Contextual Info: TLV5633C, TLV5633I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS190A – MARCH 1999 – REVISED JANUARY 2001 D D D D D D D DW OR PW PACKAGE TOP VIEW 12-Bit Voltage Output DAC Programmable Internal Reference

LM311 application notes

Abstract: LM311 LM3111 LM311 OPERATIONAL AMPLIFIER OPERATION lm311 application note LM311 application SLCS007A LM311DBLE 100 khz crystal
Contextual Info: LM111, LM211, LM311, LM311Y DIFFERENTIAL COMPARATORS WITH STROBES SLCS007A- SEPTEMBER 1973 - REVISED FEBRUARY 1992 Fast Response Times LM111 . . . J PACKAGE TOP VIEW Strobe Capability Maximum Input Bias C u rren t. . . 300 nA NC[ 1 EMIT O U T [ 2 Maximum Input Offset C u rren t. . . 70 nA

SN75LVDS81

Contextual Info: SN65LVDS86AQ, SN75LVDS86A FLATLINK RECEIVER SLLS318B – NOVEMBER 1998 – REVISED JANUARY 2001 D D D D D D D D D D D D D 3:21 Data Channel Expansion at up to 163 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to

TPS75101Q

Abstract: TPS75115Q TPS75118Q TPS75125Q TPS75133Q TPS75301Q TPS75315Q TPS75318Q TPS75325Q TPS75333Q
Contextual Info: TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS SLVS241A – MARCH 2000 – REVISED JANUARY 2001 D D D D D D

SN74251

Contextual Info: SN54251, SN54LS251 SN54S251, SN74251, SN74LS251, TIM9905 , SN74S251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDLS085 – DECEMBER 1972 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

D425G

Abstract: ACT21 SN74BCT2166
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~

Contextual Info: MC3423 OVERVOLTAGE-SENSING CIRCUIT 0 2 4 3 9 , A P R IL 1 9 7 8 - R E V I S E D M A R C H 1 9 8 8 D , JG . OR P P AC KAG E Separate O u tp u ts fo r " C ro w b a r" and Logic C irc u itry TOP V IE W vccC Program m able Tim e D elay to Eliminate Noise Triggering

ma3232c

Abstract: MAX3232 MAX3232CD MAX3232CDB MAX3232CDBR MAX3232CDR MAX3232CDW MAX3232CDWR MAX3232CPW mb3232i
Contextual Info: MAX3232 3ĆV TO 5.5ĆV MULTICHANNEL RSĆ232 LINE DRIVER/RECEIVER WITH ±15ĆkV ESD PROTECTION SLLS410I − JANUARY 2000 − REVISED JANUARY 2004 D RS-232 Bus-Pin ESD Protection Exceeds D D D D D D D D D D, DB, DW, OR PW PACKAGE TOP VIEW ±15 kV Using Human-Body Model (HBM)