D 4515 Search Results

Contextual Info: 4515B l-O F-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — The 4 5 1 5B is a 1-of-16 D ecoder/D em ultiplexer w ith four binary weignted Address C O N N E C T IO N D IA G R A M D IP TO P VIEW Inputs (A 0 - A 3 ), a Latch Enable Input (E L), an active L O W Enable Input (E) and sixteen m utually

ITS 7166

Abstract: 7166 cmos D 4515 4000B 4515B
Contextual Info: 4515B l-O F-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH D E S C R IP T IO N — T h e 4 5 1 5 B is a 1 -o f-1 6 D e c o d e r/D e m u ltip le x e r w it h fo u r b in a ry w e ig h te d A d d re ss In p u ts A 0 - A 3 , a L a tc h E n a b le I n p u t (E L ), an a c tiv e L O W E n a b le I n p u t (E ) a nd s ix te e n m u tu a lly

Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B − JUNE 1996 − REVISED JUNE 2000 D Processed to MIL-PRF-38535 D Fast Instruction Cycle Time of 30 ns and 40 ns D Source-Code Compatible With all ’C1x and D D D D D ’C2x Devices RAM-Based Operation

Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B − JUNE 1996 − REVISED JUNE 2000 D Processed to MIL-PRF-38535 D Fast Instruction Cycle Time of 30 ns and 40 ns D Source-Code Compatible With all ’C1x and D D D D D ’C2x Devices RAM-Based Operation

TMS320C50DU

Abstract: Acc 2089 mc 4069 TEXAS INSTRUMENTS, die attach datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

7217

Abstract: Acc 2089 SMJ320C50 SMJ320C50KGD TMS320C50DU
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

Acc 2089

Abstract: datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B − JUNE 1996 − REVISED JUNE 2000 D Processed to MIL-PRF-38535 D Fast Instruction Cycle Time of 30 ns and 40 ns D Source-Code Compatible With all ’C1x and D D D D D ’C2x Devices RAM-Based Operation

7166 cmos

Contextual Info: GOLDSTAR TECHNOLOGY INC-. D4E D | 4GEÖ7S7 00G17t,fl ñ | 4 0 2 8 7 5 7 G O L D S TA R TECHNOLOGY 04E INC. 01768 D T -4 7 -//-S / GD4515B l-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH DESCRIPTION - The 4515B is a 1-of-16 Decoder/Demultiptexer with four binary weighted Address

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD SPRS030
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C − JULY 1996 − REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

TMS320C50DU

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD 446526 Texas instruments military products
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

7404

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

ci 4514

Abstract: 16-LINE CD74HCT4514 CD74HCT4514E CD74HCT4515 CD74HCT4515E MS-011 4-LINE TO 16-LINE DECODERS with clock
Contextual Info: CD74HCT4514, CD74HCT4515 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314C – MAY 2002 – REVISED MAY 2003 D D D D D D E PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation Fanout (Over Temperature Range) – Standard Outputs . . . 10 LSTTL Loads

CD4514BC

Abstract: CD4514BCN CD4514BCWM CD4515BC M24B MC14514 MC14515 MS-013 N24A
Contextual Info: Revised Ja nuary 1999 S E M I C O N D U C T O R TM CD4514BC« CD4515BC 4-Bit Latched/4-to-16 Line Decoders Features • W ide supply voltage range: The C D 4514BC output active high option presents a logi­ cal “ 1” at the selected output, w hereas the C D 4515BC pre­

CD74HCT4514

Abstract: CD74HCT4514E CD74HCT4514EE4 CD74HCT4515 CD74HCT4515E CD74HCT4515EE4 CD74HCT4515EN CD74HCT4515ENE4
Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads

CD74HCT4514

Abstract: CD74HCT4514E CD74HCT4514EE4 CD74HCT4515 CD74HCT4515E CD74HCT4515EE4 CD74HCT4515EN CD74HCT4515ENE4
Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads

Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads

Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads

CD74HCT4514

Abstract: CD74HCT4514E CD74HCT4514EE4 CD74HCT4515 CD74HCT4515E CD74HCT4515EE4 CD74HCT4515EN CD74HCT4515ENE4
Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads

CD74HCT4514

Abstract: CD74HCT4514E CD74HCT4514EE4 CD74HCT4515 CD74HCT4515E CD74HCT4515EE4 CD74HCT4515EN CD74HCT4515ENE4 16-LINE
Contextual Info: CD74HCT4514, CD74HCT4515 4ĆLINE TO 16ĆLINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout Over Temperature Range D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads