D 1047 Search Results

E537

Contextual Info: Signetics 10470A 4K-Bit ECL Bipolar RAM Preliminary Specification Bipolar Memory Products PIN CONFIGURATION DESCRIPTION FEATURES T h e 10470A d e v ice is a 4 09 6 w ord s by 1 bit fully d e c o d e d R e a d /W rite Rand om A c c e s s M e m o ry , d e s ig n e d fo r high

cm 68006

Abstract: MCM10474L15 10474 MECL handbook
Contextual Info: g MCM10474*15 MCM10474*25 MOTOROLA A d v a n c e In fo r m a tio n MECL 1024 x 4 BIT R A N D O M A CCESS M E M O R Y 1024 x 4-BIT RANDO M ACCESS M EM O RY T h e M C M 10474 is a 4 0 9 6 -b it R e a d /W rite R A M o rg a n iz e d fo r 1024 w o r d s b y 4 b its . D ata is s e le c te d o r s to re d b y m e a n s o f a 10b it a d d re s s (A 0 th r o u g h A 9 ) d e c o d e d o n th e c h ip . T h e c h ip is

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT

10074A

Abstract: 1024X4 10474 10474AF 10474F
Contextual Info: BIPOLAR MEMORY DIVISION MAY 1982 4096-BIT ECL RAM 1024x4 10474/10474A Preview DESCRIPTION FEATURES The 10474/10474A device is a 1024 w o rd s by 4 b its fu lly deco d e d R ea d /W rite Ran­ d om A cce ss M em ory, d e sig n e d fo r high speed scra tch pad, co n tro l and b u ffe r s to r­

TL16PNP550A

Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY PnP AND AUTOFLOW CONTROL SLLS190B – MARCH 1995 – REVISED MARCH 1996 D D D D D D D D D D D D D D D PnP Card Autoconfiguration Sequence Compliant External Terminal-to-Bypass PnP Autoconfiguration Sequence

0A79 diode detail

Abstract: TL16PNP550A TL16C550 TL16C450 TL16C550C 10-Interrupts
Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY PnP AND AUTOFLOW CONTROL SLLS190B – MARCH 1995 – REVISED MARCH 1996 D D D D D D D D D D D D D D D PnP Card Autoconfiguration Sequence Compliant External Terminal-to-Bypass PnP Autoconfiguration Sequence

TL16PNP550A

Abstract: SGS-Thomson 2741 TL16C450 TL16C550C
Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY PnP AND AUTOFLOW CONTROL SLLS190B – MARCH 1995 – REVISED MARCH 1996 D D D D D D D D D D D D D D D PnP Card Autoconfiguration Sequence Compliant External Terminal-to-Bypass PnP Autoconfiguration Sequence

TL16PNP550A

Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY PnP AND AUTOFLOW CONTROL SLLS190B – MARCH 1995 – REVISED MARCH 1996 D D D D D D D D D D D D D D D PnP Card Autoconfiguration Sequence Compliant External Terminal-to-Bypass PnP Autoconfiguration Sequence

TL16PNP550A

Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUGĆANDĆPLAY PnP AND AUTOFLOW CONTROL ąą SLLS190B − MARCH 1995 − REVISED MARCH 1996 D PnP Card Autoconfiguration Sequence D D D D D D D D D D D D D D D On-Chip I/O Port Address Decoding D In PnP Bypass Mode, 6 External Terminals

Contextual Info: ECL 4 0 9 6 -B IT BIPOLAR SELF-TIM ED RANDOM ACCESS MEMORY FU JITSU MBM10476RL-9 4 0 9 6 -B IT BIPOLAR S ELF-TIM E D RANDOM ACCESS MEMORY D e c e m b e r, 1988 Edition 1.0 T he Fujitsu M BM 10476RL-9 Is fully d eco ded 4 0 9 6 -b it ECL s e lf-tim e d re a d /w rite

Contextual Info: TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 D Controlled Baseline D D D D D D D D D D D D D Optional Data Flow Resume by Xon Any – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 110°C

Contextual Info: TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 D Controlled Baseline D D D D D D D D D D D D D Optional Data Flow Resume by Xon Any – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 110°C

lathes

Abstract: diode td15 MS-026 S-PQFP-G48 ST16C2550 TL16C752B-EP TL16C752BTPTREP
Contextual Info: TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 D Controlled Baseline D D D D D D D D D D D D D Optional Data Flow Resume by Xon Any – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 110°C

Contextual Info: TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 D Controlled Baseline D D D D D D D D D D D D D Optional Data Flow Resume by Xon Any – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 110°C

Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

TLC16C

Abstract: TL16C450 TL16C550C TL16C750
Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

TL16C750

Abstract: TL16C450 TL16C550C SLLS191C
Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

TL16C450

Abstract: TL16C550C TL16C750
Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

Contextual Info: TL16C550D, TL16C550DI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS597D − APRIL 2004 − REVISED MAY 2006 D Programmable Auto-RTS and Auto-CTS D In Auto-CTS Mode, CTS Controls D D D D D D D D D D Transmitter In Auto-RTS Mode, RCV FIFO Contents and

Contextual Info: TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS037B – MARCH 1988 – REVISED MARCH 1996 D D D D D D D D D D D D D D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR VSS Full Double Buffering Eliminates the Need for Precise Synchronization

MS-018

Abstract: ST16C654 TL16C554 TL16C754B TL16C754BFN TL16C754BPN Dll00 t27d
Contextual Info: TL16C754B QUAD UART WITH 64ĆBYTE FIFO SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004 D ST16C654 Pin Compatible With Additional D D D D D D D D D D D Enhancements Supports Up To 24-MHz Crystal Input Clock 1.5 Mbps Supports Up To 48-MHz Oscillator Input

Contextual Info: TL16C754B QUAD UART WITH 64ĆBYTE FIFO SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004 D ST16C654 Pin Compatible With Additional D D D D D D D D D D D Enhancements Supports Up To 24-MHz Crystal Input Clock 1.5 Mbps Supports Up To 48-MHz Oscillator Input