CYPRESS NOBL 1-MBIT SRAM Search Results

Contextual Info: For Immediate Release Cypress Extends Networking SRAM Portfolio To 9 Mbit Density Family Extension Includes Best-in-Class 200 MHz, 3.3V and 2.5V Families; First Parts to Be Manufactured In High-Volume In Cypress’s New 0.2-Micron Process SAN JOSE, Calif., July 19, 2000 – Cypress Semiconductor Corp. NYSE:CY today expanded its family of

CY7C1329

Abstract: CY7C1345
Contextual Info: PRESS RELEASE CYPRESS INTRODUCES HIGH-SPEED SYNCHRONOUS SRAM FAMILY Broadens SRAM Market Coverage with New Devices SAN JOSE, Calif., August 17, 1998 - Cypress Semiconductor today introduced a family of high-speed synchronous SRAMs targeted at network and Digital Signal Processor DSP

Contextual Info: For Immediate Release Cypress Extends Networking SRAM Portfolio to 18 Mbit Density Synchronous and NoBL Memories Target Next-Generation Networking, Telecom Applications SAN JOSE, Calif., August 11, 2000 - Cypress Semiconductor Corp. NYSE:CY today extended its

SRAM 6T

Contextual Info: For Immediate Release Cypress Announces 0.15-micron Technology RAM7 Technology Achieves 8 Mb Yield with the World’s Smallest SRAM Cell SAN JOSE, Calif., August 7, 2000 – Cypress Semiconductor NYSE: CY today announced that its new 0.15-micron RAM7™ process technology has achieved functional silicon of the world’s smallest 8 Mbit

CY62136V

Abstract: CY62138V
Contextual Info: PRESS RELEASE CYPRESS'S NEW MoBL SRAMS SET NEW BENCHMARK FOR LOW-POWER 0.25-Micron Devices Offer the Industry’s Lowest Power Consumption SAN JOSE, Calif., December 7, 1998 – Cypress Semiconductor Corp. [NYSE:CY] today introduced a new family of micropower SRAMs with the industry’s lowest power consumption.

Contextual Info: Press Release CYPRESS'S NEW MoBL SRAMS SET NEW BENCHMARK FOR LOW POWER 0.25-Micron Devices Offer the Industry’s Lowest Power Consumption SAN JOSE, Calif., December 7, 1998 – Cypress Semiconductor Corp. [NYSE:CY] today introduced a new family of micropower SRAMs with the industry’s lowest power consumption. Cypress’s MoBL™ More Battery Life™

4T2R

Abstract: 4t2r sram cell
Contextual Info: For Immediate Release CYPRESS INTRODUCES 0.2-MICRON PROCESS Rapid Progress Provides Company With Competitive Advantage in Process Technology SAN JOSE, Calif., March 15, 2000 – Cypress Semiconductor today announced that its new 0.2-micron RAM6 technology is now yielding in its high-volume, 8-inch fabrication facility in Bloomington,

CY7C1371D

Abstract: CY7C1373D
Contextual Info: PRELIMINARY CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

D4C4

Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,

b1064

Abstract: CY7C1460AV33 CY7C1460AV33-250 CY7C1462AV33 CY7C1464AV33 u946 K1126 B897 J1127
Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

Contextual Info: CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

05353

Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 b669
Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■ Supports 250 MHz Bus Operations with Zero Wait States

K972

Abstract: CY7C1460AV25 CY7C1460AV25-250 CY7C1462AV25 CY7C1464AV25 u946 B897 m1124
Contextual Info: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

CY7C1461AV25

Abstract: CY7C1463AV25 CY7C1465AV25 1N611 B897
Contextual Info: CY7C1461AV25 CY7C1463AV25 CY7C1465AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

Contextual Info: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 PRELIMINARY 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.

CY7C1355C

Abstract: CY7C1357C 38T5
Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Can support up to 133-MHz bus operations with zero wait

CY7C1470BV33

Abstract: CY7C1472BV33 CY7C1474BV33
Contextual Info: CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 72 Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250 MHz bus operations with zero wait states

BWSE

Abstract: bb209a
Contextual Info: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

Contextual Info: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

Contextual Info: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

662k

Abstract: CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25
Contextual Info: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

CY7C1355C

Contextual Info: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero

Contextual Info: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero