CY7C2642KV18 Search Results
CY7C2642KV18 Datasheets (1)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C2642KV18-333BZXC |
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Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 333MHZ 165FBGA | Original | 31 |
CY7C2642KV18 Price and Stock
Infineon Technologies AG CY7C2642KV18-333BZXCIC SRAM 144MBIT PAR 165FBGA |
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CY7C2642KV18-333BZXC | 146 | 2 |
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FLIP ELECTRONICS CY7C2642KV18-333BZXCIC SRAM 144MBIT PAR 165FBGA |
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CY7C2642KV18-333BZXC | Tray | 2 |
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CY7C2642KV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports |
Original |
CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz | |
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Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports |
Original |
CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz | |
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Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports |
Original |
CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz | |
CY7C2644KV18-333BZI
Abstract: 3M Touch Systems
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Original |
144-Mbit CY7C2640KV18, CY7C2655KV18 CY7C2642KV18, CY7C2644KV18 CY7C2640KV18 CY7C2655KV18 CY7C2642KV18 CY7C2644KV18-333BZI 3M Touch Systems | |
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Contextual Info: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports |
Original |
CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz | |
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Contextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
CY7C2644KV18 144-Mbit 333-MHz | |
D2618
Abstract: 3M Touch Systems
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Original |
CY7C2644KV18 144-Mbit 333-MHz CY7C2644KV18 D2618 3M Touch Systems | |
3M Touch SystemsContextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
CY7C2644KV18 144-Mbit 333-MHz CY7C2644KV18 3M Touch Systems |