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    CY7C2161KV18 Search Results

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    3M Touch Systems

    Contextual Info: CY7C2161KV18, CY7C2176KV18 CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2161KV18, CY7C2176KV18 CY7C2163KV18, CY7C2165KV18 18-Mbit CY7C2161KV18 CY7C2176KV18 CY7C2163KV18 3M Touch Systems PDF

    CY7C2163KV18

    Abstract: 3M Touch Systems
    Contextual Info:  CY7C2161KV18, CY7C2176KV18 CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		CY7C2161KV18, CY7C2176KV18 CY7C2163KV18, CY7C2165KV18 18-Mbit 550-MHz CY7C2163KV18 CY7C2163KV18 3M Touch Systems PDF

    3M Touch Systems

    Contextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2163KV18, CY7C2165KV18 18-Mbit CY7C2163KV18 550-MHz 3M Touch Systems PDF

    3M Touch Systems

    Contextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2163KV18, CY7C2165KV18 18-Mbit CY7C2163KV18 550-MHz 3M Touch Systems PDF

    Contextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2163KV18, CY7C2165KV18 18-Mbit 550-MHz PDF

    Contextual Info: CY7C2163KV18/CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2163KV18/CY7C2165KV18 18-Mbit 550-MHz CY7C2165KV18 PDF