CY7C1473BV33 Search Results

CY7C1473BV33 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1473BV33-133AXC		Cypress Semiconductor	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture; Architecture: NoBL, Flow-through; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 3.1 to 3.6 V	Original	PDF	689.97KB	32
CY7C1473BV33-133AXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 133MHZ 100TQFP	Original	PDF		31

CY7C1473BV33 Price and Stock

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Infineon Technologies AG CY7C1473BV33-133AXC IC SRAM 72MBIT PARALLEL 100TQFP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1473BV33-133AXC	Tray			72	1 - 10 - 100 $168.44 1000 $168.44 10000 $168.44	Buy Now
Avnet Americas	CY7C1473BV33-133AXC	Tray			5	1 - 10 $166.59 100 $159.50 1000 $159.50 10000 $159.50	Buy Now
Verical ()	CY7C1473BV33-133AXC		216		3	1 - 10 $167.11 100 $157.09 1000 $147.06 10000 $147.06	Buy Now
	CY7C1473BV33-133AXC		8		3	1 - 10 $167.11 100 $157.09 1000 $147.06 10000 $147.06	Buy Now
Rochester Electronics	CY7C1473BV33-133AXC		224		1	1 $133.69 10 $133.69 100 $125.67 1000 $117.65 10000 $117.65	Buy Now
Flip Electronics	CY7C1473BV33-133AXC		2,739			1 - 10 - 100 - 1000 - 10000 -	Get Quote
FLIP ELECTRONICS CY7C1473BV33-133AXC IC SRAM 72MBIT PARALLEL 100TQFP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1473BV33-133AXC	Tray			5	1 - 10 $143.43 100 $143.43 1000 $143.43 10000 $143.43	Buy Now
Cypress Semiconductor CY7C1473BV33-133AXCT Stock
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Flip Electronics	CY7C1473BV33-133AXCT		2,739			1 - 10 - 100 - 1000 - 10000 -	Get Quote

CY7C1473BV33 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit	PDF
AN1064 Abstract: TQFP Contextual Info: CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states	Original	CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 36/4M 18/1M AN1064 TQFP	PDF
Contextual Info: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit	PDF
Contextual Info: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit CY7C1473BV33	PDF
CY7C1471BV33-133BZI Abstract: gic 1990 AN1064 CY7C1473BV33 Contextual Info: CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states	Original	CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 36/4M 18/1M CY7C1471BV33, CY7C1471BV33-133BZI gic 1990 AN1064 CY7C1473BV33	PDF
Contextual Info: CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-Through SRAM with NoBL Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■	Original	CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 72-Mbit CY7C1475BV33 36/4M 18/1M	PDF
Contextual Info: CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 72-Mbit CY7C1471BV33, CY7C1473BV33, CY7C1475BV33	PDF