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    CY7C1302DV25 Search Results

    CY7C1302DV25 Datasheets (7)

    Cypress Semiconductor
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY7C1302DV25
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 219.88KB 18
    CY7C1302DV25-100
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 221.48KB 18
    CY7C1302DV25-100BZXC
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 219.88KB 18
    CY7C1302DV25-133
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 221.48KB 18
    CY7C1302DV25-167
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 221.47KB 18
    CY7C1302DV25-167BZC
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 391.84KB 18
    CY7C1302DV25-167BZXC
    		Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF 391.84KB 18
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    CY7C1302DV25 Price and Stock

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    Infineon Technologies AG CY7C1302DV25-167BZXC

    SRAM Chip Sync Dual 2.5V 9M-bit 512K x 18 2.5ns 165-Pin FBGA Tray
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    Verical CY7C1302DV25-167BZXC 224 30
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    Avnet Americas CY7C1302DV25-167BZXC Bulk 30
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    Flip Electronics CY7C1302DV25-167BZXC 224
    • 1 $16.87
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    Cypress Semiconductor CY7C1302DV25-167BZC

    SRAM Chip Sync Dual 2.5V 9M-bit 512K x 18 2.5ns 165-Pin FBGA Tray
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    Verical () CY7C1302DV25-167BZC 220 25
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    CY7C1302DV25-167BZC 169 25
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    CY7C1302DV25-167BZC 163 25
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    CY7C1302DV25-167BZC 78 25
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    CY7C1302DV25-167BZC 65 25
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    Rochester Electronics CY7C1302DV25-167BZC 775 1
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    Flip Electronics CY7C1302DV25-167BZC 224
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    Cypress Semiconductor CY7C1302DV25-167BZXC

    QDR 9Mbit 512k x 18 2.4V - 2.6V Parallel 167MHz 2.5ns 165-BGA
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    Rochester Electronics CY7C1302DV25-167BZXC 20 1
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    Cypress Semiconductor CY7C1302DV25167BZXC

    9-MBIT BURST OF TWO PIPELINED SRAM WITH QDR ARCHITECTURE QDR SRAM, 512KX18, 2.5ns, CMOS, PBGA165
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    ComSIT USA CY7C1302DV25167BZXC 85
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    Cypress Semiconductor CY7C1302DV25-167BZXCT

    Stock
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    Flip Electronics CY7C1302DV25-167BZXCT 224
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    CY7C1302DV25 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY7C1302DV25

    Abstract: CY7C1302DV25-167 3M Touch Systems
    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 3M Touch Systems PDF

    CY7C1302DV25

    Abstract: CY7C1302DV25-167 5N25
    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 5N25 PDF

    CY7C1302DV25

    Contextual Info: CY7C1302DV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time


    Original     		CY7C1302DV25 167-MHz CY7C1302DV25 PDF

    CY7C1302DV25

    Abstract: CY7C1302DV25-167
    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 PDF

    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Functional Description Features • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 167-MHz PDF

    3M Touch Systems

    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 CY7C1302DV25 3M Touch Systems PDF

    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 167-MHz PDF

    3M Touch Systems

    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 CY7C1302DV25 3M Touch Systems PDF

    3M Touch Systems

    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		CY7C1302DV25 CY7C1302DV25 3M Touch Systems PDF

    CY7C1302DV25

    Abstract: CY7C1302DV25-167
    Contextual Info: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 PDF