CY7C1264XV18 Search Results
CY7C1264XV18 Datasheets (2)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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| CY7C1264XV18-366BZXC |
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Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 366MHZ 165FBGA | Original | 29 | |||
| CY7C1264XV18-450BZXC |
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Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 450MHZ 165FBGA | Original | 29 |
CY7C1264XV18 Price and Stock
Infineon Technologies AG CY7C1264XV18-366BZXCIC SRAM 36MBIT PAR 165FBGA |
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CY7C1264XV18-366BZXC | Tray |
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Infineon Technologies AG CY7C1264XV18-450BZXCIC SRAM 36MBIT PAR 165FBGA |
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CY7C1264XV18-450BZXC | Tray |
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CY7C1264XV18-450BZXC | Tray | 680 |
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Rochester Electronics LLC CY7C1264XV18-366BZXCIC SRAM 36MBIT PAR 165FBGA |
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CY7C1264XV18-366BZXC | Tray | 4 |
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Rochester Electronics LLC CY7C1264XV18-450BZXCIC SRAM 36MBIT PAR 165FBGA |
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CY7C1264XV18-450BZXC | Bulk | 4 |
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Cypress Semiconductor CY7C1264XV18-450BZXCSRAM Chip Sync Dual 1.8V 36M-bit 1M x 36 0.45ns 165-Pin FBGA Tray |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1264XV18-450BZXC | 174 | 25 |
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CY7C1264XV18-450BZXC | 276 | 1 |
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CY7C1264XV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: CY7C1262XV18/CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports |
Original |
CY7C1262XV18/CY7C1264XV18 36-Mbit CY7C1264XV18 | |
3M Touch Systems
Abstract: QDR cypress
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36-Mbit CY7C1262XV18, CY7C1264XV18 CY7C1262XV18 3M Touch Systems QDR cypress | |
3M Touch SystemsContextual Info: CY7C1262XV18, CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports |
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CY7C1262XV18, CY7C1264XV18 36-Mbit CY7C1262XV18 3M Touch Systems | |
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Contextual Info: CY7C1262XV18/CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports |
Original |
CY7C1262XV18/CY7C1264XV18 36-Mbit CY7C1264XV18 | |
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Contextual Info: CY7C1262XV18, CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features Separate independent read and write data ports |
Original |
CY7C1262XV18, CY7C1264XV18 36-Mbit |