CRYSTAL 50MHZ DATASHEET Search Results

ICS8R45252AKILF

Contextual Info: FemtoClock Crystal-to-CML Clock Generator ICS8R45252I DATA SHEET General Description Features The ICS8R45252I is a 3.3V,2.5V CML clock generator designed for Ethernet applications. The device synthesizes either a 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz

CISSOID S.A.

Abstract: CHT-CG-050 32.768KHZ CRYSTALS 25 MHz CRYSTAL 22pf
Contextual Info: CISSOID The SOI design Specialist CHT-CG-050 Preliminary datasheet Version 0.4 08/2005 Versatile High Temperature Clock Generator General Description Features The CHT-CG-050 is a versatile HighTemperature crystal clock generator with extended functional capabilities. The chip

LAN8720

Abstract: 1000 BASE Isolation Modules 5kV spark gap 4-12PHY IED61000-4-2
Contextual Info: LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology — — — — „ „ Key Benefits

LAN8720

Abstract: LAN8720A LAN8720 layout 2 port 10/100 ethernet transceiver RMII LAN8720A-CP LAN8720A-CP-TR LAN8720i motherboard hp 530 LAN8720AI-CP-TR
Contextual Info: LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology — — — — „ „ Key Benefits

ASM3P2853A

Abstract: oscillator 50mhz
Contextual Info: ASM3P2853A Peak EMI Reducing Solution Features • Generates an EMI optimized clock signal at output. • Input frequency: 25MHz. • Frequency outputs: o USB Clock 48MHz unmodulated o 50MHz (modulated), ±1% centre spread • Modulation rate: 39KHz. • Spread Spectrum ON/OFF control

Contextual Info: ASM3P2853A Peak EMI Reducing Solution Features • Generates an EMI optimized clock signal at output. • Input frequency: 25MHz. • Frequency outputs: o USB Clock 48MHz unmodulated o 50MHz (modulated), ±1% centre spread • Modulation rate: 39KHz. • Spread Spectrum ON/OFF control

crystal 50MHz 50ppm

Contextual Info: ASM3P2853A Peak EMI Reducing Solution Features • Generates an EMI optimized clock signal at output. • Input frequency: 25MHz. • Frequency outputs: o USB Clock 48MHz unmodulated o 50MHz (modulated), ±1% centre spread • Modulation rate: 39KHz. • Spread Spectrum ON/OFF control

Contextual Info: ASM3P2853A Peak EMI Reducing Solution Features by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The ASM3P2853A modulates the output of PLL in order to spread the bandwidth of a synthesized clock, thereby

LAN8720A

Abstract: 50mhz oscillator MAGJACK rj45 application RMII PHY LAN8700 PH-220 LAN8720 ethernet female connector pinout Ethernet Magjack lan8710a
Contextual Info: EVB8720 Evaluation Board User Manual Copyright 2010 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information

LAN8720

Abstract: LAN8720 schematic
Contextual Info: LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

LAN8720 schematic

Abstract: LAN8720 SmSC LAN8720 LAN8720i
Contextual Info: LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

LAN8720A

Abstract: LAN8720A-CP-TR ANSI X3.263-1995 standard Auto-Negotiation LAN8720A-CP Mlt-3 2 pin crystal oscillator 20mhZ LAN8720 PIN assignments of UTP cables Tx/TRANSMIT / RECEIVER FILTER
Contextual Info: LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

LAN8720A

Abstract: LAN8720A-CP LAN8720 ANSI X3.263-1995 LAN8720A-CP-TR LAN8720Ai LAN8720AI-CP RMII Specification revision 1.2 IEC61249-2-21 001111b
Contextual Info: LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

Contextual Info: PI6C49004A PCIe Gen 2 Networking Clock Generator Description Features The PI6C49004A is a clock generator device intended for PCIe® Gen2 networking applications. The device includes twelve 100MHz differential Host Clock Signal Level HCSL outputs for PCIe Gen 2, two single-ended 50MHz outputs, one singleended 32.256MHz output, and one selectable single-ended

of 33M

Abstract: 110104
Contextual Info: PI6C49004A PCIe Gen 2 Networking Clock Generator Description Features The PI6C49004A is a clock generator device intended for PCIe® Gen2 networking applications. The device includes twelve 100MHz differential Host Clock Signal Level HCSL outputs for PCIe Gen 2, two single-ended 50MHz outputs, one singleended 32.256MHz output, and one selectable single-ended

Contextual Info: XC2311 Series ETR1408_005 VCXO ICs with Built-in Variable Capacitor •GENERAL DESCRIPTION The XC2311 Series is VCXO Voltage Controlled Crystal Oscillator ICs with built-in variable capacitor diode. With the originally developed variable capacitor diode and a constant-voltage circuit built-in, the series achieves the wide

RMII Specification

Contextual Info: KSZ8081RNA/KSZ8081RND 10Base-T/100Base-TX PHY with RMII Support Revision 1.1 General Description Features The KSZ8081RNA is a single-supply 10Base-T/100BaseTX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded

LAN8720A

Abstract: LAN8710A 5173278-2 12v regulator power
Contextual Info: EVB8720 Evaluation Board User Manual Copyright 2011 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information

MAGJACK rj45 application

Abstract: 50mhz oscillator LAN8720A EVB8720 MAGJACK application
Contextual Info: EVB8720 Evaluation Board User Manual Copyright 2011 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information

LAN8720A

Abstract: LAN8720Ai LAN8720A-CP-TR IEC61249-2-21 LAN8720 SCHEMATIC 5kv pulse driver
Contextual Info: LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

ANSI X3.263-1995

Abstract: LAN8720A-CP LAN8720A-CP-TR ssd schematic schematic utp lan LAN8720AI-CP LAN8720A OS MLT 04 BLW 12v
Contextual Info: LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights „ „ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology „ — — — —

Contextual Info: LAN8720A/LAN8720Ai Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights ̈ ̈ Key Benefits Single-Chip Ethernet Physical Layer Transceiver PHY Comprehensive flexPWR Technology ̈ — — — —

CAVIUM

Abstract: CN38XX ICS8430S10I-03
Contextual Info: Clock Generator for Cavium Processors ICS8430S10I-03 DATA SHEET General Description Features The ICS8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core

Contextual Info: Standard Products UT7R995 & UT7R995C RadClockTM 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer Datasheet January 2014 power supply levels. The ternary PE/HD pin controls the synchronization of output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the