CPLD PINS TABLE Search Results

a6252

Abstract: CS144 TQ100 TQ144 XC9500XV XC95144XV
Contextual Info: XC95144XV High-Performance CPLD R DS051 v2.2 August 27, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)

Contextual Info: XC95144XV High-Performance CPLD DS051 v2.6 June 18, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)

k3402

Abstract: 131C-6 XC95144XV-7TQ144I CS144 TQ100 TQ144 XAPP361 XC9500XV XC95144XV
Contextual Info: XC95144XV High-Performance CPLD DS051 v2.7 August 21, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)

TQ144

Abstract: XAPP361 XC9500XV XC95288XV XC95288XV-10 XC95288XV-7
Contextual Info: u XC95288XV High-Performance CPLD R DS050 v2.5 August 21, 2003 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)

XC95108-15TQ100C

Abstract: XC95108-15PCG84C XC95108 XC95108-20TQ100I XC95108-15TQG100C XC95108-10PQG160I PQ100 PQG160 xc95108 tq100 XC95108-15TQ100I
Contextual Info: XC95108 In-System Programmable CPLD R DS066 v4.4 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable

XC95108-20TQ100I

Abstract: XC95108 xc95108 tq100 XC95108-15PC84C XC95108-15TQ100I PC84 XC9500 7PQ100I xc95108-7 XC95108-7PQ100C
Contextual Info: XC95108 In-System Programmable CPLD R DS066 v4.1 August 21, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable

XC9572

Abstract: xc9572-15PQ100 PC44 PC84 XC9500 XC9572-15PC44I
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.1 August 21, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XC95144

Abstract: PQ100 PQ160 TQ100 XC9500 XC95144-15TQ100C
Contextual Info: XC95144 In-System Programmable CPLD R DS067 v5.2 November 6, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable

XC9572

Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XC9572

Abstract: xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XC95144

Abstract: XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i
Contextual Info: XC95144 In-System Programmable CPLD R DS067 v5.6 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

471 E25

Abstract: XC95216-20PQ160I DS06 HQ208 PQ160 XC9500 XC95216 XC95216-10HQ208I XC95216-10PQ160 n439
Contextual Info: XC95216 In-System Programmable CPLD R DS068 v4.1 August 21, 2003 5 Product Specification Features Description • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 216 macrocells with 4,800 usable gates Up to 166 user I/O pins 5V in-system programmable

xc9536

Abstract: xc9536 vqg44 XC9536-15VQG44I XC9536-5PCG44C XC9536-15PCG44C XC9536-15VQG44C XC9536-7PCG44I XC9536-10VQ44C XC9536-10VQG44C xc9536-7pc44c
Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.3 April 3, 2006 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

XC95144

Abstract: DS06 HW130 XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 xc95144 pinout
Contextual Info: k XC9500 In-System Programmable CPLD Family R DS063 v5.1 September 22, 2003 Product Specification Features - Advanced CMOS 5V Fast FLASH technology • - Supports parallel programming of multiple XC9500 devices • High-performance - 5 ns pin-to-pin logic delays on all pins

XC95288-15HQ208I

Abstract: XC95288
Contextual Info: Product Obsolete/Under Obsolescence XC95288 In-System Programmable CPLD R DS069 v5.0 May 17, 2013 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates

XC95108

Abstract: XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I
Contextual Info: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC95108 In-System Programmable CPLD R DS066 v5.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates

xc9536

Abstract: XCN11010 xc9536 44 pin XILINX XC9536 xc9536 vqg44 xc9536-7vq44 XC9536-7VQG44I XC9536-7PCG44I XC9536-10VQ44C XC9536-15PCG44I
Contextual Info: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC9536 In-System Programmable CPLD R DS064 v7.0 May 17, 2013 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates

k1358

Abstract: COOLRUNNER-II ucf file tq144 COOLRUNNER-II ucf file XAPP399 F14152 XAPP393 XC2C64 manual XAPP 138 data CP132 -20/COOLRUNNER-II ucf file tq144
Contextual Info: Application Note: CoolRunner-II CPLDs R Assigning CoolRunner-II VREF Pins XAPP399 v1.1 July 25, 2003 Summary The flexibility of the CoolRunner -II CPLD allows users to configure any I/O pin to act as a voltage reference (VREF) pin. This document describes the different methods and underlying

XC9500

Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 xc95144 package pinout
Contextual Info: XC9500 In-System Programmable CPLD Family  January 16, 1998 Version 2.1 3* Product Information Features Family Overview • High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz • Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates

MACH131SP-5YC-7YI

Abstract: 14051k MACH Programmer PAL 007 PAL 007 A Pal programming MACH111SP MACH211SP mach210 die Vantis macro gates
Contextual Info: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

XAPP382

Abstract: JESD 85 LVCMOS25-Low-Voltage COOLRUNNER-II examples COOLRUNNER-II test circuit LVCMOS25 LVCMOS33 LVCMOS33-Low
Contextual Info: Application Note: CoolRunner-II CPLDs R CoolRunner-II I/O Characteristics XAPP382 v1.0 November 11, 2002 Summary This document is designed to be a comprehensive description of the I/O structure of the CoolRunner -II CPLD family. The I/O pins have the most dramatic externally observed

MACH211SP

Abstract: mach schematic MACH111SP
Contextual Info: MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

XAPP440

Abstract: XC9500 XC9500XL XC9500XV CoolRunner-II CPLD
Contextual Info: Application Note: CPLD R Power On Behavior of Xilinx CPLDs XAPP440 v1.0 May 25, 2006 Introduction Why Programmable Logic is Different during Power On Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pins tracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,