COUNTER 0 9 Search Results

Contextual Info: TC5026BP TC5026BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC DECADE COUNTER TC5026BP is DECADE UP COUNTER with two reset functions, RESET 9 and RESET (0) and can be used as binary counter, quinary counter or decimal counter. When two inputs of RESET (0) are set to "H", the

TC5026

Abstract: TC5026BP
Contextual Info: TC5026BP TC5026BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC DECADE COUNTER TC5026BP is DECADE UP COUNTER with two reset functions, RESET 9 and RESET (0) and can be used as binary counter, quinary counter or decimal counter When two inputs of RESET (0) are set to "H", the

TC5026

Contextual Info: TC5026BP C 2M O S DIGITAL IN T E G R A T E D CIRCUIT SIL IC O N M O N O LITH IC TC5026BP DECADE COUNTER TC5026BP is DECADE DP COUNTER with two reset functions, RESET 9 and RESET (0) and can be used as binary counter, quinary counter or decimal counter When two inputs of RESET (0) are set to "H", the

74HC393c

Abstract: OT393
Contextual Info: -File Number _ Technical Data CD54/74HC393 CD54/74HCT393 1653 HARR IS S E M I C O N D S E CT OR 27E D 4 3 02 27 1 0 0 1 7 0 2 0 7 • HAS T High-Speed CMOS Logic -1Q 0 BINARY COUNTER ¡-10, -102 - 103 BINAR* COUNTER -200 I-20, -202 -203 Dual 4-Stage Binary Counter

9316DM

Abstract: 93XX TTL logic 93S160 9316PC 9316V 93L16DM 93S16 93S16DC
Contextual Info: 10 • 16 n 0 ^ / V ' Oi D CONNECTION DIAGRAM PINOUT A d > 3 1 0 *9316 r //^ y § 3 L io • 9 3 L 1 6 ^ r , ^93810 • 93S16 0/ ^ BCD DECADE COUNTER/ 4-BIT BINARY COUNTER j|]v c c CP [2 U T C P o [T 14] Qo Pi [ 7 m p DESCRIPTION — The '10 is a high speed synchronous BCD decade counter

Truth Table 74192

Abstract: pin diagram of counter ic 74193 74193 truth table ic 74192 74192 ic Truth Table 74193 of IC 74193 TC40192BPJC40193BP IC TTL 74193 TC40192BP/TC40193BP
Contextual Info: TC40192BPJC40193BP C2M 0 S DIGITAL INTEGRATED CIRCUIT SILICO N MONOLITHIC TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) T C 4 0 1 9 2 B P / T C40193BP i synchronous 4-bit up/down

hd44780 lcd

Abstract: 16 x 2 LCD display lcd display data sheet ddram HD44780 lcd 2 x 16 HD44780 16-character lcd 2 x 12 HD44780 HD44780 display
Contextual Info: The Concise LCD Data Sheet. http://www.senet.com.au/~cpeacock Instruction NOP Clear Display Cursor Home RS RW D7 D6 D5 D4 D3 D2 D1 D0 Description 0 0 0 0 0 0 0 0 0 0 No Operation 0 0 0 0 0 0 0 0 0 1 Clears display & sets address counter to zero. 0 0 0 0 0 0 0 0 1 0 Sets address counter to zero, returns shifted

Contextual Info: blE » • SO^EMA 00243b5 740 « T 0 S 2 TC5053P.TC5054P TC5053P TC5054P C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC_ TOSHIBA L O G I C / N E N O RY 4-DIGIT UP/DOWN DECADE COUNTER 4-DIGIT UP/DOWN DECADE COUNTER T C 5 0 5 3 P / T C 5 0 5 4 P is a 4-digit decimal u p/down counter

Contextual Info: HITACHI/ L O G I C / A R R A Y S / N E M IE dË | 44c]i3503 0 0 1 D 4 4 0 7 | 92D HD74HC192 HD74HC193 10 44 0 D T~ V S -2 3 -O f # Synchronous Up/Down Decade Counter Dual Clock Lines # Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines) PIN ARRANGEMENT

Contextual Info: TC4040BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4040BP/TC4040BF 12 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS T C 4 0 4 0 B P / B F is 12 stage ripple-carry binary counter w i t h the a s y n c hronous clear function. The counter advances its counting state by falling edge

ALM18

Abstract: DS1318 J-STD-020A SS10 SS11 ALM31 ALM8 524288Hz
Contextual Info: Rev 0; 2/04 Parallel-Interface Elapsed Time Counter The DS1318 parallel-interface elapsed time counter ETC is a 44-bit counter that maintains the amount of time that the device operates from main and/or backup power or during an external event. The internal

cd40178

Abstract: pin diagram CD4017 CD4017 divide by 60 counter CD4017B cd4017 application CD4017 PIN DIAGRAM CD4017 sr flip flop operation of CD4017B ICAN-6166
Contextual Info: CD4017B, CD4022B Types CMOS Counter/Dividers High-Voltage Types 2 0 -V o lt Rating C D 4 0 1 7 B —Decade Counter w ith 10 Decoded O utputs C D 4 0 2 2 B —O ctal Counter w ith 8 Decoded O utputs The R C A -C D 4 0 1 7 B and C D 4 0 2 2 B are 5stage and 4-stage Joh n so n c o u n te rs having

ALM11

Abstract: DS1318E on delay timer circuit diagram U242
Contextual Info: Rev 0; 2/04 Parallel-Interface Elapsed Time Counter The DS1318 parallel-interface elapsed time counter ETC is a 44-bit counter that maintains the amount of time that the device operates from main and/or backup power or during an external event. The internal

DS1318E

Contextual Info: Rev 0; 2/04 Parallel-Interface Elapsed Time Counter The DS1318 parallel-interface elapsed time counter ETC is a 44-bit counter that maintains the amount of time that the device operates from main and/or backup power or during an external event. The internal

Contextual Info: HITACHI/ L OG IC / A R R A Y S/ M E M =15 D E | 4 4 ^ 2 0 3 OOlOtQM 0 | 92D HD74HC4020 # 10604 U T ~ ^ S -2 3 -/7 14-stage Binary Counter The H D 7 4 H C 4 0 2 0 is a 14 stage counter. This device is PIN ARRANGEMENT | incremented on the falling edge negative transition o f the

DS1374

Abstract: DS1374-18 DS1374-3 DS1374-33 DS1374U-18 DS1374U-3 DS1374U-33 J-STD-020A
Contextual Info: Rev 0; 4/03 2-Wire, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output Features The DS1374 is a 32-bit binary counter designed to continuously count time in seconds. An additional counter generates a periodic alarm or serves as a watchdog

TC62003P

Abstract: TC507OP TC-6200 TLR312 6-Digit BCD Counter segment TC5070P
Contextual Info: TC 5 0 7 0 P / TC5071P/TC5072P 6 D IGIT U NIVERSAL COUNTER TC5070P/TC5071P/TC5072P are 6-digit universal counter containing 6-digit memory register in addition to functions of up/down counting, data presetting, zero

Contextual Info: □ MN1870877 MN1870877 • Type 1 ROM x8-bit 8K 1 RAM (x8-bit) 256 1 Minimum Instruction Execution Time 2/3 dividing 0.5ps (at 4.5 to 5.5V, 12MHz) | Interrupts •RESET | Timer Counter Tim er Counter 0 : 8-bit x 1 • External 0 • External 1 • Timer 0

Contextual Info: MN102L490A Type MN102L490A ROM x× 8-bit External RAM (×× 8-bit) 3K Package LQFP100-P-1414 *Lead-free Minimum Instruction Execution Time With Main Clock operated Interrupts • RESET • Watchdog • Timer counter 0 to 5 • Timer counter 6 to 7 • Timer counter 6 to 7 compare capture A • Timer counter 6 to 7 compare capture B

LS93

Abstract: LS90 T74LS90 LS92 T74LSXX bcd counter 7490 bcd counter 74 90
Contextual Info: $90/ 92/93 890/92/93 LS90 DECADE COUNTER LS92 DIVIDE-BY-TWELVE COUNTER LS93 4-BIT BINARY COUNTER DESCRIPTION 1 T h e T 5 4 L S 9 0 /T 7 4 L S 9 0 , T 5 4 L S 9 2 /T 7 4 L S 9 2 and T 5 4 L S 9 3 /T 7 4 L S 9 3 are high-speed 4-bit ripple ty­ pe counters partitioned into two sections. Each

AD09

Abstract: AD08 AD-04
Contextual Info: MN102L490A Type MN102L490A ROM x× 8-bit External RAM (×× 8-bit) 3K Package LQFP100-P-1414 *Lead-free Minimum Instruction Execution Time With Main Clock operated Interrupts • RESET • Watchdog • Timer counter 0 to 5 • Timer counter 6 to 7 • Timer counter 6 to 7 compare capture A • Timer counter 6 to 7 compare capture B

Contextual Info: MN102L490A Type MN102L490A ROM x× 8-bit External RAM (×× 8-bit) 3K Package LQFP100-P-1414 *Lead-free Minimum Instruction Execution Time With Main Clock operated Interrupts • RESET • Watchdog • Timer counter 0 to 5 • Timer counter 6 to 7 • Timer counter 6 to 7 compare capture A • Timer counter 6 to 7 compare capture B

opal

Abstract: equivalent M 393 54HCT393 74HCT 74HCT393 74SC393 7803b ripple counter
Contextual Info: H C T/S C 393 Dual 4 Bit Binary Ripple Counter Preliminary * High Speed 74H C T Device Parameter Standard (74SC ) Military (54HCT) Dual 4-Bit Binary Ripple Counter 74H C T393 74S C 3 9 3 54H C T393 Operating Voltage Range ( ° Cl - 4 0 to + 8 5 - 4 0 to + 8 5

TC4510BP

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4510BP/BF TC4510BP/TC451OBF PRESETTABLE BCD UP/DOHN COUNTER TC4510BP/BF is UP/DOWN decade counter having asynchronous RESET and PRESET functions. When RESET input is set to "H" level, the content of counter is reset to "0" and when RESET is set to "L"