CONVOLUTION ENCODER Search Results

CONVOLUTION ENCODER Result Highlights (5)

Part	Manufacturer	Description	Download
54LS147J/B	Rochester Electronics LLC	54LS147 - Priority Encoders	PDF
DM54148J	Rochester Electronics LLC	DM54148J - Priority Encoder	PDF
AM7992BJC	Rochester Electronics LLC	AM7992B - Manchester Encoder/Decoder, PQCC28	PDF
AM7992BPC	Rochester Electronics LLC	AM7992B - Manchester Encoder/Decoder, PDIP24	PDF
AM7992BDC	Rochester Electronics LLC	AM7992B - Manchester Encoder/Decoder, CDIP24	PDF

CONVOLUTION ENCODER Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
MA1916 Abstract: szy 21 Contextual Info: APRIL 1995 MA1916 DS3590-3.2 MA1916 RADIATION HARD REED-SOLOMON & CONVOLUTION ENCODER The purpose of the MA1916 is to encode serial data to allow error correction when the data is transmitted over a noisy communication link. As the name suggests, the unit contains	Original	MA1916 DS3590-3 MA1916 szy 21	PDF
16psk block diagram Abstract: Implementation of convolutional encoder differential encoder for psk viterbi convolution 16PSK Convolutional CS3310 convolution encoder uPI Semiconductor CS3310TK Contextual Info: CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated Application Specific Virtual Components ASVC	Original	CS3310 CS3310 silicon256 DS3310-a 16psk block diagram Implementation of convolutional encoder differential encoder for psk viterbi convolution 16PSK Convolutional convolution encoder uPI Semiconductor CS3310TK	PDF
viterbi convolution Abstract: 16-PSK 16psk Convolutional Encoder Convolutional DS3310 CS3310 CS3310AA CS3310TK 16psk block diagram Contextual Info: CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated Application Specific Virtual Components ASVC	Original	CS3310 CS3310 DS3310 viterbi convolution 16-PSK 16psk Convolutional Encoder Convolutional CS3310AA CS3310TK 16psk block diagram	PDF
56B3 Abstract: 5.6B3 FFG1157 vhdl convolution coding Turbo Code LogiCORE IP License Terms block interleaver in modelsim umts turbo encoder Contextual Info: LogiCORE IP 3GPP Turbo Encoder v4.1 DS319 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table This version of the Turbo Convolution Code TCC encoder is designed to meet the 3GPP mobile communication system specification [Ref 1], [Ref 2].	Original	DS319 56B3 5.6B3 FFG1157 vhdl convolution coding Turbo Code LogiCORE IP License Terms block interleaver in modelsim umts turbo encoder	PDF
Contextual Info: N EC ELECTRONICS INC b?E D • L427SES DD3^31S 321 HINECE JJPD78356 Family ftiPD78355/356/P356 NEC Electronics Inc. 16-/8-Bit, K-Series Microcontrollers W ith A/D Converter and Convolution Capability September 1993	OCR Scan	L427SES JJPD78356 ftiPD78355/356/P356) 16-/8-Bit, PD78355, /JPD78356, PD78P356 16-bit 16-/8-bit	PDF
A333J Contextual Info: b427S25 0043413 W . \|\\| E C NEC Electronics Inc. «NECE #iPD78356 Family yPD78355/356/P356 16-/8-Blt, K-Series Microcontrollers With A/D Converter and Convolution Capability Preliminary September 1993 Description Features The /JPD78355, pPD78356, and /JPD78P356 are	OCR Scan	b427S25 iPD78356 yPD78355/356/P356) 16-/8-Blt, /JPD78355, pPD78356, /JPD78P356 16-/8-bit 16-bit A333J	PDF
szy 21 Abstract: ce 65 s encoder MA1916 seal msg XG404 convolution encoder Contextual Info: MA1916 MA1916 Radiation Hard Reed-Solomon & Convolution Encoder Replaces June 1999 version, DS3590-4.0 DS3590-5.0 January 2000 The purpose of the MA1916 is to encode serial data to allow error correction when the data is transmitted over a noisy communication link. As the name suggests, the unit contains	Original	MA1916 DS3590-4 DS3590-5 MA1916 szy 21 ce 65 s encoder seal msg XG404 convolution encoder	PDF
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS APRIL 1995 MA1916 DS3590-3.2 MA1916 RADIATION HARD REED-SOLOMON & CONVOLUTION ENCODER The purpose of the MA1916 is to encode serial data to allow error correction when the data is transmitted over a noisy	Original	MA1916 DS3590-3 MA1916	PDF
Turbo decoder Xilinx Abstract: Turbo Decoder lte turbo encoder xilinx lte TURBO decoder LTE Turbo decoder XILINX,ISE XMP020 turbo encoder design using xilinx design of lte turbo encoder xilinx TURBO decoder Contextual Info: 3GPP LTE Turbo Decoder v2.0 XMP020 June 24, 2009 Product Brief Introduction General Description The Turbo Convolution Code TCC decoder core is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels. The TCC decoder is designed	Original	XMP020 Turbo decoder Xilinx Turbo Decoder lte turbo encoder xilinx lte TURBO decoder LTE Turbo decoder XILINX,ISE turbo encoder design using xilinx design of lte turbo encoder xilinx TURBO decoder	PDF
ce 65 s encoder Abstract: convolution encoder MA1916 Contextual Info: MA1916 MA1916 Radiation Hard Reed-Solomon & Convolution Encoder Replaces January 2000 version, DS3590-5.0 DS3590-5.1 July 2002 The purpose of the MA1916 is to encode serial data to allow error correction when the data is transmitted over a noisy communication link. As the name suggests, the unit contains	Original	MA1916 DS3590-5 MA1916 ce 65 s encoder convolution encoder	PDF
vhdl code for Circular convolution Abstract: vhdl convolution coding XAPP551 Viterbi Trellis Decoder viterbi convolution vhdl code for lte channel coding vhdl code lte Convolutional Encoder ModelSim 6.5c convolutional Contextual Info: Application Note: All Virtex and Spartan FPGA Families Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting XAPP551 v2.0 July 30, 2010 Summary Author: Michael Francis Many digital communication standards employ convolution coding as a means of forward error	Original	XAPP551 vhdl code for Circular convolution vhdl convolution coding XAPP551 Viterbi Trellis Decoder viterbi convolution vhdl code for lte channel coding vhdl code lte Convolutional Encoder ModelSim 6.5c convolutional	PDF
xilinx TURBO decoder Abstract: DS275 Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11 Contextual Info: 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 Product Specification Features Applications • Drop-in module for Spartan -3, Spartan-3E, This version of the TCC Turbo Convolution Code decoder is designed to meet the 3GPP2 mobile communication system specification [1].	Original	DS275 CDMA2000/3GPP2 xilinx TURBO decoder Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11	PDF
XAPP551 Abstract: viterbi convolution X551 Contextual Info: Application Note: All Virtex and Spartan FPGA Families R XAPP551 1.0 February 14, 2005 Summary Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting Authors: Bill Wilkie and Beth Cowie Many digital communication standards employ Convolution Coding as a means of forward error	Original	XAPP551 technique51 XAPP551 viterbi convolution X551	PDF
0060B Abstract: MA1916 Contextual Info: MA1916 MA1916 Radiation Hard Reed-Solomon & Convolution Encoder Replaces January 2000 version, DS3590-5.0 DS3590-5.1 July 2002 The purpose of the MA1916 is to encode serial data to allow error correction when the data is transmitted over a noisy communication link. As the name suggests, the unit contains	Original	MA1916 DS3590-5 MA1916 0060B	PDF

SZY 23 Contextual Info: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ APRIL 1995	Original	MA1916 DS3590-3 MA1916 SZY 23	PDF
Convolutional Puncturing Pattern Abstract: Convolutional Encoder viterbi convolution ds248 Contextual Info: Convolutional Encoder v3.0 DS248 v1.5 March 28, 2003 Product Specification Features Applications • This core can be used in a wide variety of convolutional encoding applications and is typically used to encode data for use with the Viterbi decoder. •	Original	DS248 Convolutional Puncturing Pattern Convolutional Encoder viterbi convolution ds248	PDF
XILINX vhdl code REED SOLOMON encoder decoder Abstract: "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator convolution encoder datasheet Reed-Solomon Decoder viterbi convolution Contextual Info: Reed-Solomon Encoder January 10, 2000 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features	Original	4000X, XILINX vhdl code REED SOLOMON encoder decoder "Galois Field Multiplier" verilog Reed-Solomon Decoder verilog code XILINX vhdl code download REED SOLOMON encoder decoder XILINX vhdl code download REED SOLOMON vhdl code for 8-bit parity generator vhdl code for a 9 bit parity generator convolution encoder datasheet Reed-Solomon Decoder viterbi convolution	PDF
Schematic convolution interleaving Abstract: convolution encoder ISS 98 PC84 convolution encoders XCS10-3 X7964 viterbi convolution Contextual Info: iss_reed_sol.fm Page 77 Tuesday, February 24, 1998 5:41 PM Reed-Solomon Encoder January 12, 1998 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664	Original		PDF
"Galois Field Multiplier" verilog Abstract: XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bit interleaver Reed-Solomon Decoder verilog code xilinx vhdl code for digital clock 4005XL viterbi convolution Contextual Info: Reed-Solomon Encoder February 22, 1999 Product Specification AllianceCORE Facts Integrated Silicon Systems, Ltd. 50 Malone Rd Belfast BT9 5BS Northern Ireland Phone: +44 1232 664664 Fax: +44 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com Features	Original	4000XL, "Galois Field Multiplier" verilog XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bit interleaver Reed-Solomon Decoder verilog code xilinx vhdl code for digital clock 4005XL viterbi convolution	PDF
QED1000 Abstract: digital FIR Filter using frequency sampling method circuit diagram for iir and fir filters adsp 21xx processor advantages VLSI implementation of FIR filters c code for interpolation and decimation filter chebyshev 0.01dB AD1892 iir filter diagrams FIGURE 9 CIRCUIT DIAGRAM OF FIR AND IIR FILTERS Contextual Info: DIGITAL FILTERS SECTION 6 DIGITAL FILTERS • Finite Impulse Response FIR Filters ■ Infinite Impulse Response (IIR) Filters ■ Multirate Filters ■ Adaptive Filters 6.a DIGITAL FILTERS 6.b DIGITAL FILTERS SECTION 6 DIGITAL FILTERS Walt Kester INTRODUCTION	Original	ADSP-21000 QED1000 digital FIR Filter using frequency sampling method circuit diagram for iir and fir filters adsp 21xx processor advantages VLSI implementation of FIR filters c code for interpolation and decimation filter chebyshev 0.01dB AD1892 iir filter diagrams FIGURE 9 CIRCUIT DIAGRAM OF FIR AND IIR FILTERS	PDF
2b1q decoder Abstract: 3B2T 3b2t encoding A-133 MSAN-127 2b1q encoding Contextual Info: MSAN-127  2B1Q Line Code Tutorial Application Note ISSUE 2 March 1990 Introduction Line Coding In August 1986 the T1D1.3 Now T1E1.4 technical subcommittee of the American National Standards Institute chose to base their standard for the ISDN Basic Access on the Network Side of the NT1 on an	Original	MSAN-127 2b1q decoder 3B2T 3b2t encoding A-133 MSAN-127 2b1q encoding	PDF
3B2T Abstract: AMI encoding Biphase decoder pulse code interval encoding tutorial transformer power A-133 MSAN-127 2b1q encoding Contextual Info: MSAN-127  2B1Q Line Code Tutorial Application Note ISSUE 2 March 1990 Introduction Line Coding In August 1986 the T1D1.3 Now T1E1.4 technical subcommittee of the American National Standards Institute chose to base their standard for the ISDN Basic Access on the Network Side of the NT1 on an	Original	MSAN-127 3B2T AMI encoding Biphase decoder pulse code interval encoding tutorial transformer power A-133 MSAN-127 2b1q encoding	PDF
ALP57 Abstract: SRC1000 Contextual Info: Audio Codec For DVD Record ADAV832 Preliminary Technical Data FEATURES PRODUCT OVERVIEW Stereo Analog to Digital Converter ADC Supports 48/96 kHz Sample Rates 102 dB Dynamic Range Single-Ended Input Automatic Level Control Stereo Digital to Analog Converter (DAC)	Original	ADAV832 ADAV832 PR04754-0-3/04 ALP57 SRC1000	PDF
1amz Abstract: code excited linear predictive ippiRGBToYUV420 Winograd A838 adaptive algorithm subband matlab feig sample code fft algoritm H263 SA-1110 Contextual Info: Intel Integrated Performance Primitives for the Intel® StrongARM* SA-1110 Microprocessor Reference Manual May 4, 2001 Version 1.01 Order Number: 278288-004 This document describes the Intel R Integrated Performance Primitive (IPP) software libraries for the Intel® StrongARM* Development Platform. It	Original	SA-1110 SA-1110 ToneGetSizeQ15 ToneQ15 TriangleGetSizeQ15 TriangleInitQ15 TriangleQ15 WinBlackmanQ15 WinKaiserQ15 1amz code excited linear predictive ippiRGBToYUV420 Winograd A838 adaptive algorithm subband matlab feig sample code fft algoritm H263	PDF

CONVOLUTION ENCODER Search Results

CONVOLUTION ENCODER Result Highlights (5)

CONVOLUTION ENCODER Datasheets Context Search

MA1916

16psk block diagram

viterbi convolution

56B3

A333J

szy 21

Turbo decoder Xilinx

ce 65 s encoder

vhdl code for Circular convolution

xilinx TURBO decoder

XAPP551

0060B

SZY 23

Convolutional Puncturing Pattern

XILINX vhdl code REED SOLOMON encoder decoder

Schematic convolution interleaving

"Galois Field Multiplier" verilog

QED1000

2b1q decoder

3B2T

ALP57

1amz