CODED MARK INVERSION 1993 Search Results

Contextual Info: CD22103A 3 ÎAfHSS CMOS HDB3 High Density Bipolar 3 Transcoder for 2.048/8.448 Mb/s Transmission Applications March1993 Features Description • HDB3 Coding and Decoding fo r Data Rates from 50Kh/s to 10Mb/s In a Manner Consistent w ith CCITT G703 Recommendations

CD22103AE

Abstract: snes HDB3 coding coded mark inversion 1993 CD22103AD HDB3 to nrz NRZ to HDB3 CD22103
Contextual Info: HARRIS SEfllCOND SECTOR blE D • 3 hVSS » 43G2571 0G47231 Ô77 ■ HAS CD22103A CMOS HDB3 High Density Bipolar 3) Transcoder for 2.048/8.448 Mb/s Transmission Applications March1993 Features Description • HDB3 Coding and Decoding for Data Rates from

Contextual Info: H A R R HC-5560 IS S E M I C O N D U C T O R PCM Transcoder March 1993 Features Description • Single 5V Supply. 10mA Typ. The HC-5560 digital line transcoder provides encoding and decoding of pseudo ternary line code substitution schemes.

Contextual Info: SSI 78P2362 stmsmbns 34.368 Mbit/s Line Interface A TDK Group/Company Preliminary Data December 1993 DESCRIPTION FEATURES The SSI 78P2362 is a line interface transceiver IC intended for 34.368 Mbit/s applications. The receiver has a very wide dynamic range and is designed to

Contextual Info: skew swim SSI 78P2361 STS-1 Line Interface A TDK Group/Company December 1993 DESCRIPTION FEATURES The SSI 78P2361 is a line interface transceiver IC intended for STS-1 51.84 Mbit/s applications. The receiver has a very wide dynamic range and is designed to accept B3ZS-encoded Alternate-Mark

TR-TSY-000499

Contextual Info: SSI 78P236 M DS-3 Line Interface m M k n ts A TDK Group/Company December 1993 DESCRIPTION FEATURES The SSI 78P236 is a line interface transceiver IC intended for DS-3 44.736 Mbit/s applications. The receiver has a very wide dynamic range and is designed to accept B3ZS-encoded Alternate-Mark

DP8492

Abstract: 1-1420 switch free circuit diagram of hard disk nrzi C1995 DP84900 DP84900M DP84900MS MSA20 DP8490
Contextual Info: June 1993 General Description Features The DP84900 is designed to perform the encoding and decoding for disk memory systems It is designed to interface directly with National Semiconductor’s integrated read channel circuits such as the DP8492 This Encoder

78P2361

Abstract: 78P2362 78P7200 GR-253-CORE PE-65969 PT5045 center tapped transformer
Contextual Info: SSI 78P7200 S m iM h n s DS-3/E3/STS-1 Line Interface with Receive Equalizer " A TDK Group/Company September 1995 DESCRIPTION FEATURES The SSI 78P7200 is a line interface transceiver IC intended for STS-1 51.84 Mbit/s , DS-3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a

Terpene Defluxer

Abstract: coded mark inversion 1993 TM622 RG6 coaxial cable db loss at 1 ft 139,264 TM311DVA t-330sct J 6812 TM-622 213B
Contextual Info: Copperhead Series CMI Transceiver line interface modules for SONET/SDH applications E4/STM-1 and STM-1 low profile .200” Compact, one package transceiver line interface modules for interfacing to the most widely used CMI chip sets for E4/STM-1 and STM-1 applications

TDK 78P7200-IH

Abstract: 78P2361 78P2362 78P7200 GR-253-CORE PE-65969 PT5045 signal detection circuit "peak hold" constant vol PEAK DETECTOR CIRCUIT SHORT NOTE
Contextual Info: 78P7200 DS-3/E3/STS-1 Line Interface With Receive Equalizer March 1998 DESCRIPTION FEATURES The 78P7200 is a line interface transceiver IC intended for STS-1 51.84 Mbit/s , DS-3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a very wide dynamic range and is

TDK 78P7200-IH

Contextual Info: 78P7200 DS3/E3/STS-1 Line Interface With Receive Equalizer March 1998 DESCRIPTION FEATURES The 78P7200 is a line interface transceiver IC intended for STS-1 51.84 Mbit/s , DS3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a very wide dynamic range and is

Contextual Info: 1 MP Macroprocessor User's Manual Program Development Support Software FIRST EDITION ISSUE DATE:Aug. 1993 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information

TDK 78P7200-IH

Abstract: TRW coded digital signals capacitor 12-24 pF Variable pin-compatible replacement
Contextual Info: &TDK. TSC 78P7200 DS-3/E3/STS-1 Line Interface with Receive Equalizer TDK SEMICONDUCTOR CORP. October 1996 DESCRIPTION FEATURES The TSC 78P7200 is a line interface transceiver IC intended forSTS-1 51.84 Mbit/s , DS-3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a

78P7200-IH/F

Abstract: 78P7200-IH RLF2 78P7200 GR-253-CORE PE-65969 PT5045 ANSI T1.102
Contextual Info: 78P7200 E3/DS3/STS-1 Line Interface Unit DATA SHEET JULY 2005 DESCRIPTION FEATURES The 78P7200 is a line interface transceiver IC intended for STS-1 51.84 Mbit/s , DS3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a very wide dynamic range and is

MAC66K

Abstract: m66301 MSM66301 e50 f01 MSM66301 NX8 lts 542 7 segment display 1000H OLMS-66K RAS66K 7 segment display LTS 542
Contextual Info: 1 MAC66K Assembler Package User's Manual Program Development Support Software Relocatable Assembler Linker Librarian Object Converter RAS66K RL66K LIB66K OH66K THIRD EDITION ISSUE DATE:Nov. 1993 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or

102KZ

Abstract: PE65387
Contextual Info: S e m ic o n d u c to r C o rp o ra tio n CS6158A Rev H Process Change Notification Date: August 31, 1993 Rev H of the CS6158A is a three-layer, yield-enhancement revision of the mask set that made no changes to form , fit or function. Repeated below are long-standing corrections to the CS6158A data sheet. There were no design changes

Contextual Info: DS3112 TEMPE T3 E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 MUX www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § FUNCTIONAL DIAGRAM Operates as M13 or E13 multiplexer or as standalone T3 or E3 framer Flexible multiplexer can be programmed for

Contextual Info: DS3112 TEMPE T3 E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 MUX www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § FUNCTIONAL DIAGRAM Operates as M13 or E13 multiplexer or as standalone T3 or E3 framer Flexible multiplexer can be programmed for

DS3112

Abstract: G747 GR-499-CORE LTCLK10 143b
Contextual Info: DALLAS SEMICONDUCTOR DS3112 TEMPE Preliminary Data Sheet V3 September 1, 1999 DALLAS SEMICONDUCTOR DS3112 TEMPE T3 E3 MultiPlexEr 3.3V T3 / E3 Framer & T1 to T3 (M13) / E1 to E3 (E13) / E1 to T3 (G.747) Multiplexer Preliminary Data Sheet Version 3 September 1, 1999

HT 12E APPLICATION

Abstract: t2/e2 DS3112 DS3112N G747 GR-499-CORE GR-820-CORE e2 framer E19 LB2
Contextual Info: PRELIMINARY DS3112 www.dalsemi.com TEMPE T3 E3 Multiplexer 3.3V T3 / E3 Framer and M13/E13/G.747 MUX FEATURES FUNCTIONAL DIAGRAM Operates as M13 or E13 multiplexer or as stand alone T3 or E3 framer Flexible multiplexer can be programmed for multiple configurations including:

DS3112

Abstract: DS3112N G747 GR-499-CORE LB1901 rbps2
Contextual Info: PRELIMINARY DS3112 TEMPE T3 E3 Multiplexer 3.3V T3 / E3 Framer and M13/E13/G.747 MUX www.dalsemi.com FEATURES FUNCTIONAL DIAGRAM Operates as M13 or E13 multiplexer or as stand alone T3 or E3 framer Flexible multiplexer can be programmed for multiple configurations including:

CD4046 tone decoder

Abstract: ST811 PLL CD4046 application CD4046 pll application note CD4046 vco rotary binary coder S3507 S35061 S-350-7
Contextual Info: MAM I S3506I/S35071/S3507AI Industrial Temperature — is t a n d a r d p r o d u c t s CMOS Single Chip ¡¿-Law/ A-Law Synchronous Combo Codecs With Filters Features February 1993 • Encoder has Dual-Speed Auto-Zero Loop for Fast Acquisition on Power-up

syn 7580

Abstract: D2396 LT917 BT806 Bt8069 80X88 D16C BTT9170KPJ btt9170kp
Contextual Info: BtT9170 Intelligent T1 Controller Product Description Distinguishing Features The BtT9170 Intelligent T1 Controller is a microprocessor MPU controlled device which implements a T1 interface between the multiplexed digital DS1 signal and the PCM highway of digital voice and data system equipment. The

Contextual Info: DIGITAL VIDEO & DIGITAL SIGNAL PROCESSING IC Handbook GEC P L E S S E Y SEMICONDUCTORS Foreword GEC Plessey Semiconductors has substantially increased its activities in Digital Video developments since the last issue of this handbook in December 1993 . A