CMS L06 Search Results

ADSP-2185N

Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

AD73322

Abstract: ADSP-2100 ADSP-2181 ADSP-2186L ADSP-2189M ADSP-2186LBST-160 ADSP-2186LBCA-160 ADSP-2186LBST-133 ADSP-2186LKST-160
Contextual Info: a FEATURES Performance 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby

Contextual Info: a FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby

001C

Abstract: AD1847 ADSP-2100 ADSP-2181 ADSP-2186L ADSP-2186LBST-160 ADSP-2186LBCA-160 ADSP-2186LBST-133 ADSP-2186LKST-160
Contextual Info: a FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby

Contextual Info: DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every

AD73322

Abstract: ADSP-2100 ADSP-2188N ADSP-2189M 3029 IFC
Contextual Info: PRELIMINARY TECHNICAL DATA a DSP Microcomputer ADSP-2188N Preliminary Technical Data PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

Contextual Info: a Preliminary Technical Data DSP Microcomputer ADSP-2186M FEATURES Performance • • • • • • • 13.3 ns Instruction Cycle Time @ 2.5 Volts internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle