CLOCK RECOVERY Search Results

TDM 5510

Abstract: 5501 7 segment
Contextual Info: Application Note MSAN-171 TDM Clock Recovery from CBR-OverATM Links Using the MT90500 ISSUE 1 Contents 1. 2. 3. 4. 5. 6. 7. Introduction Plesiochronous Clock Applications Generalized Clock Recovery Synchronous Method Physical Layer Clock Adaptive Clock Recovery Method

8B10B

Abstract: AN1925 APP1925 serial link clock signal Signal Path Designer
Contextual Info: Maxim > App Notes > FIBER-OPTIC CIRCUITS Keywords: HFTA-07.0: Precision Reference Clock Usage in Clock and Data Recovery Circuits Mar 13, 2003 APPLICATION NOTE 1925 HFTA-07.0: Precision Reference Clock Usage in Clock and Data Recovery Circuits Applications for clock data recovery CDR abound in telecommunications, optical transceivers, data and storage

VSC8162

Abstract: STM-16
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Product Preview 2.488Gb/s SONET / SDH 1:16 Demux with Clock Recovery VSC8162 Features • 1:16 Integrated Demux with Clock Recovery • Differential Low Speed Outputs • Recovered Clock and Data Available • Single-ended Reference Clock

real time clock using I2C protocol application

Abstract: remote controlled real time clock MSAN-198 MPC8260 MT9045 MT90869 MT90880
Contextual Info: MSAN-198 Application Note Performing Clock Recovery for Circuit Emulation when using the MT90880 Contents AN5789 1.0 Circuit Emulation Services over a Packet Network 1.1 Leased Line Provision 1.2 Regenerating the Clock 2.0 Clock Recovery Techniques 2.1 Adaptive Clock Recovery

STM-64

Abstract: VSC1235 VSC1236
Contextual Info: TRANSPORT PRODUCTS VSC1235, VSC1236 9.9 to 12.5 Gbps 16:1 Multiplexer with Clock Multiplier Unit and Demultiplexer with Clock Recovery Chip Set BENEFITS: VSC1235 Full-rate Clock output for use with Clocked Laser Drivers or in RZ Signal Generation Extremely Low Clock-data Skew

Contextual Info: TAN-059 July 18, 2006 DS-1/E1 Line Recovered Clock PLL Timing INTRODUCTION The analog interface of Exar LIU devices contains a CDR Clock and Data Recovery block that recovers a clock signal from the incoming data. This clock signal derives its timing and phase from

Contextual Info: Agilent N4877A Clock Data Recovery and Demultiplexer 1:2 Agilent N1075A Optical Pick-Off/Converter Agilent N1070A Optical Clock Recovery Solution Version 1.0 Data Sheet Figure 1. N1070A optical clock data recovery solution consisting of N4877A clock data recovery and demultiplexer 1:2 and N1075A optical pick-off/converter

T7032PC

Abstract: T7032 T7032PL MOC 361
Contextual Info: Dala Sheet January 1992 âA T& T Microelectronics T7032 Clock Recovery and Data Retiming Circuit Features Description • Clock recovery and data retiming The AT&T T7032 Clock Recovery and Data Retiming Circuit operates over an 800 kHz to 52 MHz frequency range and provides clock recovery, data

Contextual Info: PRELIMINARY DATASHEET MOST CLOCK INTERFACE 5V80001 Description Features The 5V80001 is a high performance clock interface for use in MOST® Media Oriented Systems Transport enabled systems. It can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a

Contextual Info: * PROGRAMMABLE WIDE-BAND CLOCK SYNTHESIZER WITH CLOCK RECOVERY CVÊUFBnV SEMICONDUCTOR FEATURES • ■ 3.3V and 5V power supply options ■ SONET/SDH/ATM and Fiber Channel compatible ■ Clock and data recovery from 35Mbps up to 1.25Gbps NRZ data stream ■ Two on-chip PLLs: One for clock generation and

USE-OSC32768

Abstract: crystal oscillator marking crystal oscillator 32.768 crystal oscillator 32.768 marking 1090 MHz oscillator
Contextual Info: New Product .768kHzKHZ Crystal Oscillator 32.768 Clock Oscillator 32.768kHz Crystal Oscillator Crystal Oscillator OSC01 Crystal Oscillator Pb USE-OSC32768 ϮApplications Clock and Data Recovery SX-2520 ●Applications 4'' Pb ●Features Clock and Data Recovery

Contextual Info: 622 Mbps Clock and Data Recovery IC ADN2806 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator

ECU 206

Abstract: NTE123A
Contextual Info: 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY SY87700V FEATURES • 3.3V and 5V power supply options ■ SONET/SDH/ATM compatible ■ Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream, clock generation from 32Mbps to 175Mbps ■ Two on-chip PLLs: one for clock generation and

RC Phase shift Oscillator

Abstract: UM97Z8X0104 differential Pierce Oscillator XTAL1
Contextual Info: USER’S MANUAL 3 CHAPTER 3 CLOCK 3.1 CLOCK The Z8 MCU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and a clock buffer. Figure 3-1 illustrates the clock

S3014

Abstract: 3411N
Contextual Info: DEVICE SPECIFICATION S3014 S3014 SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT BiCMOS PECL CLOCK GENERATOR SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and CCITT specifications for jitter tolerance

637e

Abstract: IC CLOCK ADN2806 ADN2806ACPZ ADN2806ACPZ-500RL7 ADN2806ACPZ-RL7 GR-253-CORE MO-220-VHHD-2 A6SUB
Contextual Info: 622 Mbps Clock and Data Recovery IC ADN2806 FEATURES GENERAL DESCRIPTION Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C interface to access optional features

Contextual Info: DEVICE SPECIFICATION S3026 S3026 SONET/SDH/ATM CLOCK RECOVERY UNIT BiCMOS PECL CLOCK GENERATOR SONET/SDH/ATM CLOCK RECOVERY UNIT GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter transfer

A6SUB

Abstract: ADN2806 ADN2806ACPZ GR-253-CORE MO-220-VHHD-2
Contextual Info: 622 Mbps Clock and Data Recovery IC ADN2806 FEATURES GENERAL DESCRIPTION Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C interface to access optional features

GR-253-CORE

Abstract: MO-220-VHHD-2 ADN2806 ADN2806ACPZ
Contextual Info: 622 Mbps Clock and Data Recovery IC ADN2806 FEATURES GENERAL DESCRIPTION Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C interface to access optional features

ENE3127B

Abstract: NDK America STCD1040RDM6F STCD1020 STCD1020RDG6E STCD1030 STCD1040 TDFN12 TDFN-10 iact
Contextual Info: STCD1020, STCD1030, STCD1040 Multichannel clock distribution circuit Features • 2, 3 or 4 outputs buffered clock distribution ■ Single-ended sine wave or square wave clock input and output ■ Individual clock enable for each output ■ Lower fan-out on clock source

ECP-U1C154MA5

Abstract: ECP-U1C684MA5 GR-1244-CORE GRM42-2X5R106K10 MK1575-01 MK2069 FS15-12
Contextual Info: DATASHEET MK1575-01 CLOCK RECOVERY PLL Description Pre-Configured Input/Output Frequency Combinations: The MK1575-01 is a clock recovery Phase-Locked Loop PLL designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to

157501GL

Contextual Info: DATASHEET MK1575-01 CLOCK RECOVERY PLL Description Pre-Configured Input/Output Frequency Combinations: The MK1575-01 is a clock recovery Phase-Locked Loop PLL designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to

ENE3127B

Abstract: NDK America ndk TCXO STCD1020 STCD1020RDG6E STCD1030 STCD1040 STCD1040RDM6F TDFN12
Contextual Info: STCD1020, STCD1030, STCD1040 Multichannel clock distribution circuit Features • 2, 3 or 4 outputs buffered clock distribution ■ Single-ended sine wave or square wave clock input and output ■ Individual clock enable for each output ■ Lower fan-out on clock source

ene31

Contextual Info: STCD1020, STCD1030, STCD1040 Multichannel clock distribution circuit Features • 2, 3 or 4 outputs buffered clock distribution ■ Single-ended sine wave or square wave clock input and output ■ Individual clock enable for each output ■ Lower fan-out on clock source