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    CLOCK GENERATOR FOR 4040 Search Results

    CLOCK GENERATOR FOR 4040 Result Highlights (5)

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    CLOCK GENERATOR FOR 4040 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+3hz/12hz/1920-ppplication PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+3hz/12hz/1920-ppplication PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+2hz/12hz/19 PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


    Original
    cdc5806scas760a54-mhzhz/54+3hz/12hz/1920-ppplication PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


    Original
    cdc5806scas760a54-mhzhz/54+3hz/12hz/1920-pd PDF

    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+3hz/12hz/1920-pstruments PDF

    CDC5806

    Abstract: MTSS001C
    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+3hz/12hz/19mtss001c PDF

    CDC5806

    Abstract: CDC5806PW CDC5806PWR CDC5806PWRG4 MTSS001C
    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+6hz/12hz/19cdc5806pwcdc5806pwrcdc5806pwrg4mtss001c PDF

    CDC5806

    Abstract: CDC5806PW CDC5806PWG4 CDC5806PWR CDC5806PWRG4 MTSS001C
    Contextual Info: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate


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    cdc5806scas760a54-mhzhz/54+7hz/12hz/19cdc5806pwcdc5806pwg4cdc5806pwrcdc5806pwrg4mtss001c PDF

    Contextual Info: CDC5806 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS SCAS760A − MARCH 2004 − REVISED MAY 2004 features D High Performance Clock Generator D Clock Input Compatible With D D Max D PLLs are Powered Down, if No Valid D D D REF_IN Clock < 5 MHz) is Detected or the


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    cdc5806scas760a54-mhz PDF

    Contextual Info: CDCD5704 www.ti.com SCAS823A – DECEMBER 2006 – REVISED JANUARY 2008 Rambus XDR™ CLOCK GENERATOR FEATURES 1 • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface • Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823a300-mhz667-mhz PDF

    Contextual Info: CDCD5704 www.ti.com SCAS823A – DECEMBER 2006 – REVISED JANUARY 2008 Rambus XDR™ CLOCK GENERATOR FEATURES 1 • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface • Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823a300-mhz667-mhz PDF

    Contextual Info: CDCE949-Q1 www.ti.com SCAS891 – FEBRUARY 2010 PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS Check for Samples: CDCE949-Q1 FEATURES 1 • • • • Qualified for Automotive Applications Member of Programmable Clock Generator


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    cdce949-q1scas891cdce913/cdcel913cdce925/cdcel925+3cdce937/cdcel937cdce949ieee139p PDF

    SSC31

    Abstract: fs37 SSC3020 CDCE949 CDCE949QPWRQ1 ssc-32 SSC16 ssc24 SSC3120
    Contextual Info: CDCE949-Q1 www.ti.com SCAS891 – FEBRUARY 2010 PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS Check for Samples: CDCE949-Q1 FEATURES 1 • • • • Qualified for Automotive Applications Member of Programmable Clock Generator


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    cdce949-q1scas891cdce913/cdcel913cdce925/cdcel925+10cdce937/cdcel937cdce949ssc31fs37ssc3020cdce949qpwrq1ssc-32ssc16ssc24ssc3120 PDF

    Contextual Info: CDCE949 CDCEL949 www.ti.com SCAS844D – AUGUST 2007 – REVISED MARCH 2010 Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs Check for Samples: CDCE949, CDCEL949 FEATURES • 1 • Member of Programmable Clock Generator Family


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    cdce949cdcel949scas844dcdce913/cdcel913+3cdce925/cdcel925cdce937/cdcel937cdce949/cdcel949 PDF

    CDCE913

    Abstract: CDCEL913
    Contextual Info: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator


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    cdcel913-q1scas888cdce913/cdcel913cdce925/cdcel925+4cdce937/cdcel937cdce949/cdcel949cdce913cdcel913 PDF

    Contextual Info: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator


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    cdcel913-q1scas888cdce913/cdcel913cdce925/cdcel925+2cdce937/cdcel937cdce949/cdcel949 PDF

    Contextual Info: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator


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    cdcel913-q1scas888cdce913/cdcel913cdce925/cdcel925+2cdce937/cdcel937cdce949/cdcel949 PDF

    B0137

    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823300-mhz667-mhz+1b0137 PDF

    B0137

    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


    Original
    cdcd5704scas823300-mhz667-mhz+1b0137 PDF

    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823300-mhz667-mhz PDF

    Rambus XDR

    Abstract: CDCD5704 TSSOP-28 t0132
    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823300-mhz667-mhz+3rambus xdrtssop-28t0132 PDF

    XDR Rambus

    Abstract: CDCD5704 TSSOP-28 B0137
    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823300-mhz667-mhz+3xdr rambustssop-28b0137 PDF

    CDCD5704

    Abstract: TSSOP-28 t0132 B0137
    Contextual Info: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers


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    cdcd5704scas823300-mhz667-mhz+3tssop-28t0132b0137 PDF