CLOCK EDGE Search Results

clock oscillators

Abstract: Raltron Electronics part marking guide crystal
Contextual Info: HIGH FREQUENCY, LOW JITTER CLOCK OSCILLATOR ` FAST TURNAROUND CLOCK OSCILLATOR XCO FEATURES + DESCRIPTION The XCO clock series is a cutting edge family of low to high  Fast Turnaround Ships Within Days frequency, low jitter output, single or multi - frequency clock

LK A W01

Contextual Info: RGB640 11.0 Pin Descriptions 11.1 Summary Description Number Video Reference Clock Input 1 External Video Clock Input 2 Auxiliary Reference Clock Input 1 Auxiliary PLL Output Clock Output 1 Divided Dot Clock Output 1 Serial Clock Output 1 Load Clock Input

AN1545

Abstract: MPC9993 MPC99J93
Contextual Info: Freescale Semiconductor Technical Data MPC99J93 DATA Rev 3, SHEET 05/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC99J93 MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock

Contextual Info: DATA SHEET MPC99J93 Freescale Semiconductor Technical Data Rev 3, 05/2005 MPC99J93 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC99J93 (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock

Contextual Info: Freescale Semiconductor Technical Data DATAMPC9993 SHEET Rev 3, 06/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC9993 MPC9993 The MPC9993 is a PLL clock driver designed specifically for redundant clock

AN1545

Abstract: MC88915 MPC9448 MPC9993
Contextual Info: DATA SHEET MPC9993 Freescale Semiconductor Technical Data Rev 3, 06/2005 MPC9993 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC9993 (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock

CY7C361

Contextual Info: CY7C361 PRELIMINARY s CYPRESS SEMICONDUCTOR A programmable on-board clock doubler allows the device to operate at 125 MHz in­ ternally based on a 62.5-MHz input clock reference. The clock doubler is not a phase-lockedloop. It produces an internal pulse on each edge of the external clock.

CDC9163

Abstract: 430VX
Contextual Info: CDC9163 PC CLOCK SYNTHESIZER/DRIVER WITH SDRAM CLOCK SUPPORT SCAS574 – JULY 1996 D D D D D D D D D Clock Generation for Pentium/430VX Motherboards Twelve Host Clock Outputs With Programmable Frequency Six PCI Clock Outputs One Serial Bus 48-MHz Clock

Contextual Info: xr XRK79993 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRK79993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

MC74AC273

Abstract: MC74AC373 74AC MC74AC374 MC74AC377 MC74ACT377 74act377 motorola
Contextual Info: MC74AC377 MC74ACT377 Octal D FlipĆFlop with Clock Enable OCTAL D FLIP-FLOP WITH CLOCK ENABLE The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

Contextual Info: # Dual J-K Flip-Flops with Preset This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accom­

XRK7955

Contextual Info: xr XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7955 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

XRK79993IQ

Contextual Info: xr XRK79993 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER SEPTEMBER 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRK79993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

XRK79892

Abstract: XRK79892IQ
Contextual Info: xr XRK79892 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER SEPTEMBER 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

XRK7988

Contextual Info: xr XRK7988 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

XRK7933

Contextual Info: xr XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7933 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and

R16-14

Contextual Info: HD74HC107 # Dual J-K Flip-Flops with Clear This flip -flo p is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and

semi catalog

Abstract: j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952
Contextual Info: Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide 1 Clock Generator Data Sheets 2 QUICCClock Generator Data Sheets 3 Failover or Redundant Clock Data Sheets 4 Clock Synthesizer Data Sheets

XRK79892

Abstract: XRK79892IQ
Contextual Info: xr XRK79892 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER JANAUARY 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

transistor x1

Abstract: IDT49FCT805 49FCT805A 49FCT806 AN-82 IDT49FCT805A IDT49FCT806 IDT74FCT244A
Contextual Info: CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS  Integrated Device Technology, Inc. APPLICATION NOTE-82 CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS APPLICATION NOTE AN-82 By Michel Conrad INTRODUCTION WHAT IS CLOCK SKEW ?

Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock

405C

Abstract: LVEP224 NB100LVEP224 Socket IC 80 pin LQFP
Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock

AN1545

Abstract: MPC9993 MPC99J93
Contextual Info: Freescale Semiconductor Technical Data MPC99J93 Rev 3, 05/2005 Intelligent Dynamic Clock Switch IDCS PLL Clock Driver MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from