CLOCK DOWN Search Results

Clock ic

Contextual Info: CLOCK IC DECISION TREE CLOCK IC Clock Generator PLL Computing Server Mobile Network/Consumer Desktop Clock Multiplier PCI Express LVPECL Spread Spectrum Clock Generator Input Frequency DIE Voltage Spread Input Multiplication VCXO IC 2.5V With PLL Down 3.3V

Contextual Info: RC001 RC001 Redundant Clock Module Positive ECL Compatible Differential Output U.S. Patent 6,970,045 Rev E Description The Redundant Clock Module is intended to supply highly reliable fixed clock reference. • Clock Redundancy • Zero Downtime • HALT/HASS Verified

Contextual Info: RC001 RC001 Redundant Clock Module Positive ECL Compatible Differential Output U.S. Patent 6,970,045 Rev E Description The Redundant Clock Module is intended to supply highly reliable fixed clock reference. • Clock Redundancy • Zero Downtime • HALT/HASS Verified

Contextual Info: ICS2694 Integrated Circuit Systems, Inc. Motherboard Clock Generator Features Applications • Low cost - eliminates multiple oscillators and Count Down Logic • CPU clock and Co-processor clock • Hard Disk and Floppy Disk clock Primary VCO has 16 Mask Programmable frequencies

AN1545

Abstract: MPC9993 MPC99J93
Contextual Info: Freescale Semiconductor Technical Data MPC99J93 DATA Rev 3, SHEET 05/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC99J93 MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock

Contextual Info: DATA SHEET MPC99J93 Freescale Semiconductor Technical Data Rev 3, 05/2005 MPC99J93 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC99J93 (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock

Contextual Info: Freescale Semiconductor Technical Data DATAMPC9993 SHEET Rev 3, 06/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC9993 MPC9993 The MPC9993 is a PLL clock driver designed specifically for redundant clock

AN1545

Abstract: MC88915 MPC9448 MPC9993
Contextual Info: DATA SHEET MPC9993 Freescale Semiconductor Technical Data Rev 3, 06/2005 MPC9993 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC9993 (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock

M600

Contextual Info: MoBL Clock M300/M600 Three-PLL Programmable Clock Generator for Portable Applications Features Benefits • Device Operating Voltage Options: ❐ MoBL Clock M300 Family: 1.8V ❐ MoBL Clock M600 Family: 2.5V, 3.0V, or 3.3V ■ Selectable clock output voltages for both MoBL Clock M300

Contextual Info: CDC5806 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS SCAS760A − MARCH 2004 − REVISED MAY 2004 features D High Performance Clock Generator D Clock Input Compatible With D D Max D PLLs are Powered Down, if No Valid D D D REF_IN Clock < 5 MHz) is Detected or the

100mhz crystal decoupling

Contextual Info: 19-5214; Rev 0; 4/10 Spread-Spectrum Clock Generators The MAX31C80/MAX31D80 are spread-spectrum clock generators that contain a phase-locked loop PLL that generates a 2MHz to 134MHz clock from an input clock or crystal. The PLL can provide a spread-spectrum down-dithered (MAX31D80) or center-dithered

Contextual Info: 19-5214; Rev 0; 4/10 Spread-Spectrum Clock Generators The MAX31C80/MAX31D80 are spread-spectrum clock generators that contain a phase-locked loop PLL that generates a 2MHz to 134MHz clock from an input clock or crystal. The PLL can provide a spread-spectrum down-dithered (MAX31D80) or center-dithered

M3000

Abstract: LF24A M6000 MO-220
Contextual Info: MoBL Clock M3000/M6000 Three-PLL Programmable Clock Generator for Portable Applications Features Benefits • Device Operating Voltage Options: ❐ MoBL Clock M3000 Family: 1.8V ❐ MoBL Clock M6000 Family: 2.5V, 3.0V, or 3.3V ■ Selectable clock output voltages for both MoBL Clock M3000

Contextual Info: 19-5214; Rev 0; 4/10 Spread-Spectrum Clock Generators The MAX31C80/MAX31D80 are spread-spectrum clock generators that contain a phase-locked loop PLL that generates a 2MHz to 134MHz clock from an input clock or crystal. The PLL can provide a spread-spectrum down-dithered (MAX31D80) or center-dithered

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL Clock Driver MC88921 With Power-Down/Power-Up Feature The MC88921 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It Is designed to provide clock distribution for CISC microprocessor

Contextual Info: CY27020 Spread Spectrum Clock Generator Spread Spectrum Clock Generator Features Functional Description • Supports clock requirements for printers The CY27020 clock generator provides a low EMI clock output for printers. It features spread spectrum technology, a

CL1101

Abstract: CL1502 610 108 001 PHSOSCK17/M16/M26/M36 SL 100 power transistor sl 100 transistor YN 2 SL 220 CL117 CL166 PHSOSCK17
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PMSCKDC 2/4/6/8 2.5V CMOS Level Input Clock Driver PMSCKDCD(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Down PMSCKDCU(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Up PMSCKDS(2/4/6/8)

application notes of TF 513

Abstract: PHSOSCK17 PHSOSCK27 STD130
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

CL 2181

Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

Contextual Info: xr XRK79993 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRK79993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _SCAS379B - FEBRUARY 1993 - REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock

SL 2042

Abstract: CL 2181 27570 TR-2207 PHSOSCK17 STD150 TF011 CL118 CL 0805 samsung 1622
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PMSCKDC 2/4/6/8 2.5V CMOS Level Input Clock Driver PMSCKDCD(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Down PMSCKDCU(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Up PMSCKDS(2/4/6/8)

XRK7955

Contextual Info: xr XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7955 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

Contextual Info: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994- REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vqc Distributes Differential LVPECL Clock