CIRCUITRY INTERLEAVING Search Results

NCP5425 D

Abstract: NCP5425 NCP5425DB NCP5425DBG NCP5425DBR2 NCP5425DBR2G NTD110N02RT4 NTD60N02R pHfet
Contextual Info: NCP5425 Dual Synchronous Buck Controller The NCP5425 is a highly flexible dual buck controller with internal gate drivers that can be used with two input power supplies and one or two outputs in multiple configurations. The part contains all the circuitry required for two independent synchronous dual NFET buck

32 pins qfn 5x5 footprint

Abstract: phase converters diagrams simple 12v to 19v converter ISL6244 ISL6244CR ISL6244CRZ ISL6244HR ISL6244HRZ MO-220 TB379
Contextual Info: ISL6244 Data Sheet November 2003 FN9106.1 Multi-Phase PWM Controller Features The ISL6244 provides core-voltage regulation by driving 2 to 4 interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in

DAC ic 0808 pin diagram

Abstract: 16 pin DAC ic 0808 pin diagram application of NON INVERTING AMPLIFIER ISL6569ACB-T ISL6569ACR ISL6569ACR-T MO-220 HIP6601B ISL6569A ISL6569ACB
Contextual Info: ISL6569A Data Sheet January 2003 FN9092 Multi-Phase PWM Controller Features The ISL6569A provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output

HIP6601B

Abstract: ISL6569 ISL6569CB ISL6569CB-T ISL6569CR ISL6569CR-T MO-220 DAC ic 0808 pin diagram
Contextual Info: ISL6569 Data Sheet August 2002 FN9085.3 Multi-Phase PWM Controller Features The ISL6569 provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output

HIP6601B

Abstract: ISL6569A ISL6569ACB ISL6569ACB-T ISL6569ACR ISL6569ACR-T MO-220 DAC ic 0808 pin diagram
Contextual Info: ISL6569A Data Sheet November 2003 FN9092.1 Multi-Phase PWM Controller Features The ISL6569A provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output

interleaving

Abstract: AB-069 ADC603 circuitry Interleaving
Contextual Info: INTERLEAVING ANALOG-TO-DIGITAL CONVERTERS by Jerry Horn, 602 746-7413 the sample rate (due to the offset error) and the other with a frequency of half the sample rate minus the frequency of the original input signal (due to the gain error). It is tempting when pushing the limits of analog-to-digital

DAC ic 0808 pin diagram

Abstract: HIP6601B ISL6559 ISL6559CB ISL6559CB-T ISL6559CR ISL6559CR-T MO-220
Contextual Info: ISL6559 Data Sheet August 2002 FN9084.3 Multi-Phase PWM Controller Features The ISL6559 provides core-voltage regulation by driving 2 to 4 interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in

texas instruments handbook

Abstract: handbook texas instruments SSTL-15 texas instruments the voltage regulator handbook EIA-644 SSTL-18 HSTL standards
Contextual Info: Section II. I/O Interfaces This section provides information on Stratix III device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: Revision History Altera Corporation

GMSK wireless data transmission

Abstract: BT 199 DDD11 FX589 FX589D5 FX589DW FX589P bt 137 good FX589 Application Notes
Contextual Info: eooq = 3 CML Semiconductor Products PRODUCT INFORMATION FX589 Low-Voltage/High-Speed GMSK Modem Publication D/589/5 December 1995 Features Applications • • Wireless LAN/Modems • Handy Data Terminals • Low-Power Wireless Data Link for PCs, Laptops and Printers

558-5999-q9

Abstract: PH406466 PACKAGE Delta LF8731 KS8999 factory test 5 port
Contextual Info: KS8999 Micrel KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.14 KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset

LF3320

Abstract: interleave D213 200H 201H D113 D114 D115 D214 D215
Contextual Info: Interleaved Filtering with the LF3320 Application Note DEVICES INCORPORATED Interleaved Filtering with the LF3320 DEVICES INCORPORATED Optimized to support interleaved data sets, the LF3320’s architecture provides users with a cost-effective singlechip 32-tap FIR filter while significantly simplifying system design.

remote control rx tx

Abstract: MX589DW bt 151 600 MX019 MX589 MX589P MX589TN
Contextual Info: MX589 COMMUNICATION SEMICONDUCTORS DATA BULLETIN High Speed GMSK Modem Features Applications • Data Rates from 4kbps to 64kbps • Point of Sale Terminals • Full or Half Duplex Gaussian Minimum Shift Keying GMSK Operation • Low Power Wireless Data Link for PCs,

Contextual Info: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.3 Document last updated for Altera Complete Design Suite version:

Contextual Info: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.1 Document last updated for Altera Complete Design Suite version:

Contextual Info: 10-Bit, 300 MSPS High Speed TxDAC+” D/A Converter AD9751 Preliminary Technical Data ANALOG ► DEVICES 7-1-99 FEATURES DVDD 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD: 75 dB Internal 2x Clock Doubler/PLL Differential or Single Ended Clock Input

SSTL-15

Abstract: SSTL-18 112Rx BGA1152 mini-lvds connector
Contextual Info: 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices SIII51009-1.1 Introduction The Stratix III device family offers up to 1.25-Gbps differential I/O capabilities to support source-synchronous communication protocols such as Utopia, Rapid I/O , XSBI, SGMII, SFI, and SPI.

RIFA 100n x2

Abstract: 2N2222 to92 Zener diode 1N4148 rifa 100n 86H-7416 Voltech PM1200 transistor Bc 2n2222 Transistor 2N2222 NPN TO92 2n2907 to92 DE1E3KX472MA5B
Contextual Info: AND8356 Performance of a 300 W, Wide Mains Interleaved PFC Driven by the NCP1601 Prepared by: Joël TURCHI, ON Semiconductor http://onsemi.com APPLICATION NOTE Overview ON Semiconductor to reduce the switching losses without sacrificing the PF and THD performance.

Contextual Info: For Immediate Assistance, Contact Your Local Salesperson B U R R -B R O W N « E PCM63P 1 DEMO BOARD AVAILABLE See Appendix A for more information. Colinear 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • • • • The PCM63P is a precision 20-bit digital-to-analog

1B01

Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD9755

Abstract: AD9755AST AD9755ASTRL AD9755-EB P1B10 MHz VCO C0225
Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD9751

Abstract: AD9751AST AD9751-EB AWG2021 DG2020 HP8644 ofdm equations 8075an
Contextual Info: FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD9755-EB

Abstract: AD9755 AD9755AST P1B10
Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

ISL6323

Abstract: ISL6323CRZ ISL6323IRZ ISL6614 TB347 ISEN122 ISEN224
Contextual Info: ISL6323 Hybrid SVI/PVI Data Sheet October 21, 2008 FN9278.4 Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors Features The ISL6323 dual PWM controller delivers high efficiency and tight regulation from two synchronous buck DC/DC

Contextual Info: LSI LOGIC L64767 SMATV QAM Encoder Preliminary Datasheet Introduction LSI Logic’s L64767 is a highly integrated device comprising digital television CoreWare pro­ cessing elements for energy dispersal, Reed-Solomon encoding, convolutional interleaving,