CHN 53 B Search Results

ES62CB5

Abstract: chn 6 shaft encoder H7X-20 BHK 16.05A.0500-I2-5 BHK 16.24K20-I2-5 BHK 16.24K1024-B2-9 BHK 16.05A1000-B6-5
Contextual Info: Incremental hollow shaft encoder BHK features • miniaturized hollow shaft encoder with extended pulse range • radial cable connection or connector • through shaft mounting ø 6 mm or end shaft mounting ø 12 mm general data voltage supply max. supply current

15 ca CHN

Abstract: DIN916 e239 L4562
Contextual Info: Incremental hollow shaft encoder BRIH – EcoMag features • miniaturized hollow shaft encoder with wide pulse range • radial cable connection or connector • end shaft mounting up to ø 12 mm general data ambient conditions voltage supply 5 VDC ±10% 05A

CHN 534

Abstract: CHN 533 CHN 650 B/transistor chn 534 CHN 450 transistor CHN d5332 transistor chn 115
Contextual Info: µA Dual Rail-to-Rail +2.5V to 5.5V, 230µ Voltage-Output DACs with Parallel Interface Preliminary Technical Data AD5332/AD5333/AD5342/AD5343* a FEATURES AD5332: Dual 8-Bit DAC in 20-Lead TSSOP AD5333: Dual 10-Bit DAC in 24-Lead TSSOP AD5342: Dual 12-Bit DAC in 28-Lead TSSOP

Contextual Info: MCP3914 3V Eight-Channel Analog Front End Features: Description: • Eight Synchronous Sampling 24-bit Resolution Delta-Sigma Analog-to-Digital A/D Converters The MCP3914 is a 3V eight-channel Analog Front End (AFE), containing eight synchronous sampling deltasigma, Analog-to-Digital Converters (ADC), eight

Contextual Info: 80C24 Technology Incorporated AutoDUPLEX CMOS Ethernet Interface Adapter PRELIMINARY DATA SHEET December 10, 1996 Functional Features • Low Power CMOS Technology Ethernet Serial Note: Check for latest Data Sheet revision before starting any designs. Interface Adapter with Integrated Manchester

Contextual Info: MCP3913 3V Six-Channel Analog Front End Features: Description: • Six Synchronous Sampling 24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -107 dBc Total Harmonic Distortion THD (up to 35th Harmonic), 112 dBFS SFDR for Each Channel • Enables 0.1% Typical Active Power Measurement

AD11C

Abstract: MD09 IDT7M9602
Contextual Info: IDT MOBILE WINCHIP PROCESSOR MODULE ADVANCE INFORMATION IDT7M9602 Integrated Device Technology, Inc. FEATURES: • • • • • IDT W inC hip Processor technology with Internal/bus frequencies of 180/60 or 200/66 512K Secondary level cache of pipeline burst SRAM

ym 3511

Contextual Info: 16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH IDT74 FST163232 ADVANCE INFORMATION driver. These devices connect input and output ports through an n-channel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts and the resistance between input and output ports is small. With­

transistor TO-92 crc 13002

Abstract: transistor CHN 137
Contextual Info: CYIL2SM1300AA LUPA-1300-2 High speed CMOS Image Sensor Features n 1280 x 1024 active pixels SXGA resolution . n 14 µm2 square pixels [based on the high-fill factor active pixel sensor technology of FillFactory (US patent No. 6,225,670 and others)] n On-chip 10-bit ADCs

HC-2501P-COG

Abstract: RH1S VR01 HC2501P Trident Displays HC350
Contextual Info: Mu. oy.fi. Trident Displays Data HC-2501P-COG Trident Displays Limited Perrywood Business Park Honeycrock Lane Redhill Surrey RH1 5JQ Tel: 01737 780 790 Fax: 01737 771 908 E-mail: sales@trident-uk.co.uk Website: www.trident-uk.co.uk MODEL NO. : HC-2501P-CQG

MCP3911

Abstract: CHN G4 112 CHN 952 CHN 943 MCP3911A0 CHN G4 CHN G4 216 CHN G4 221
Contextual Info: MCP3911 3.3V Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -106.5 dBc Total Harmonic Distortion THD (up to 35th harmonic), 111 dB SFDR for Each Channel • 2.7V - 3.6V AVDD, DVDD

Contextual Info: MCP3911 3.3V Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -106.5 dBc Total Harmonic Distortion THD (up to 35th harmonic), 111 dB SFDR for Each Channel • 2.7V – 3.6V AVDD, DVDD

CHN G4 942

Abstract: CHN G4 140 CHN G4 CHN G4 221 CHN G4 310 CHN G4 216 CHN 948
Contextual Info: MCP3911 3.3V Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -106.5 dBc Total Harmonic Distortion THD (up to 35th harmonic), 111 dB SFDR for Each Channel • 2.7V – 3.6V AVDD, DVDD

uPD424210AL

Abstract: ADV601 ADV601LC CCIR-656 H261 Philips SAA7111 CCTV DISTRIBUTION NETWORK diagram CCTV wireless functional diagram hm514265cj-60 ef97
Contextual Info: a Ultralow Cost Video Codec ADV601LC GENERAL DESCRIPTION FEATURES 100% Bitstream Compatible with the ADV601 Precise Compressed Bit Rate Control Field Independent Compression 8-Bit Video Interface Supports CCIR-656 and Multiplexed Philips Formats General Purpose 16- or 32-Bit Host Interface With

Contextual Info: 1 2 3 5 4 28 6 7 8 a A i_ n vO P l a s f i c o v er mol de d RJI C a b l e AWG 22/ 7 M a t i n g f a c e RJ45 a c c o r d i n g to IEC 6 0 6 0 B - 7 X 4 3 Loading-Plan: Shield - T r a n s m i s s i o n p r o p e r t i e s in a c c o r d a n c e wi t h I SO/1 EC 1 1 8 0 1: 20 02 : C l a s s D.

CHN G4 141

Abstract: CHN G4 112 chn 711 chn 832 CHN 833 CHN G4 136 CHN G4 119 TS22 CHN G4 140 XRT86VL32IB
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JANUARY 2007 REV. 1.2.2 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

CHN G4 136

Abstract: chn 711 CHN G4 141 CHN G4 124 CHN G4 137 CHN 423
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JANUARY 2007 REV. 1.2.2 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

Contextual Info: ATM CELL BASED NON-BLOCKING SINGLE CHIP ADVANCED INFORMATION IDT77V500 SWITCH CONTROLLER Integrated D e v i e TechnoJogy, l ie . • Available in a 100-pin Thin Plastic Quad Flat Pack TQFP FEATURES: • Single chip controller for IDT77V400 Switching Memory

CHN G4 120

Abstract: chn 752 chn 731 CHN G4 MCP3901 chn 751 chn G4 210 PIC32 chn 608 Rogowski
Contextual Info: MCP3901 Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture • 91 dB SINAD, -104 dBc Total Harmonic Distortion THD (up to 35th harmonic), 109 dB Spurious-free

TC804CLS

Abstract: tc804 17B02 ERO 1841 capacitor ROE 1840
Contextual Info: T E LE D Y NE COMPONENTS 3bE D A TlTbüE 0007104 0 - T S I- lO WTELEDYNE COMPONENTS ~ V2L TC804 12-BIT |xP-COMPATIBLE MULTIPLEXED A/D CONVERTER FEATURES GENERAL DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The TC804 is a 12-bit plus sign and over-range analog

CHN 550

Abstract: CHN 545 chn 710 CHN 712 chn 538 CHN 431 CHN 709 CHN 741 chn 738 chn 648 equivalent
Contextual Info: R&S ZNC/ZND Vector Network Analyzers User Manual ;xíÇ2 User Manual Test & Measurement 1173.9557.02 ─ 26 This manual describes the following vector network analyzer types: ● R&S®ZNC3 (2 ports, 9 kHz to 3 GHz, N connectors), order no. 1311.6004K12

chn 627

Abstract: chn 810 CHN 725 diode chn 610 chn 630 b244a k 3511 CHN 420 CHN 727
Contextual Info: 16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH IDT74FST163232 ADVANCE INFORMATION In te g ra te d D evice T echnology, Inc. driver. These devices connect input and output ports through an n-channel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts and

Contextual Info: HDSL Systems HTU Applications HDSL is a simultaneous full duplex transmission scheme which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber communications interfaces. A complete HDSL system con­

CHN G4 136

Abstract: CHN G4 319 CHN G4 117 CHN G4 CHN 922 equivalent CHN 703 SLC96 alarm frame format chn 711 chn 037 digital clock with alarm using 8051
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.0 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,