CH249 Search Results

Contextual Info: LogiCORE IP SPI-4.2 v13.0 DS823 March 20, 2013 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is

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Abstract: NC154 74LV128 NC168 NC108 NC143 C495 transistor NC164 NC132 NC130
Contextual Info: ZLAN-57 ZL50211 2048 Channel VEC System Application Note Contents August 2003 The design contained within this document is intended as reference material only, and not as a fully qualified system. It is intended to be used as a starting point for a customer design.

BRAM

Abstract: zynq axi ethernet software example
Contextual Info: LogiCORE IP SPI-4.2 v11.2 DS823 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Features • Up to 700 MHz DDR on SPI-4.2 interface supporting 1.4 Gbps pin pair total bandwidth • • • • • • • • • • • • • • •

ch249

Contextual Info: LogiCORE IP SPI-4.2 v12.2 DS823 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is