CD74HCT10 Search Results
CD74HCT10 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy | 
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| CD74HCT10M96 | 
 
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High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 | 
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| CD74HCT109E | 
 
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | 
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| CD74HCT10MT | 
 
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High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 | 
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| CD74HCT10M | 
 
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High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 | 
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| CD74HCT10M96G4 | 
 
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High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 | 
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CD74HCT10 Datasheets (91)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| CD74HCT10 | 
 
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High Speed CMOS LogicTriple 3-Input NAND Gate | Original | 32.55KB | 6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT10 | 
 
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High Speed CMOS Logic Triple 3-Input NAND Gate | Original | 39.98KB | 6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107 | 
 
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Dual J-K Flip-Flop with ResetNegative-Edge Trigger | Original | 45.14KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107 | 
 
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 55.87KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107E | 
 
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CD74HCT107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 630.46KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107E | 
 
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 55.87KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107E | 
 
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 454.56KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107E | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 33.05KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107E96 | 
 
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 45.14KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107EE4 | 
 
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CD74HCT107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 630.46KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107EE4 | 
 
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Original | 290.99KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107EE4 | 
 
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 454.56KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107EG4 | 
 
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Integrated Circuits (ICs) - Logic - Flip Flops - IC FF JK TYPE DUAL 1BIT 14DIP | Original | 632.95KB | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT107M | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 33.05KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| CD74HCT109 | 
 
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Original | 46.64KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT109 | 
 
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Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | Original | 57.17KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT109E | 
 
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CD74HCT109 - High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 440.61KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT109E | 
 
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HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | Original | 57.16KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT109E | 
 
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Dual J-inverted K Flip-Flop with Set and Reset Positive-Edge Trigger | Original | 155.36KB | 11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT109E | 
 
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 457.52KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CD74HCT10 Price and Stock
Texas Instruments CD74HCT10M96IC GATE NAND 3CH 3-INP 14SOIC | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CD74HCT10M96 | Digi-Reel | 2,334 | 1 | 
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CD74HCT10M96 | 1,594 | 
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CD74HCT10M96 | 1,000 | 
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CD74HCT10M96 | 12,130 | 1 | 
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Texas Instruments CD74HCT107EIC FF JK TYPE DBL 1-BIT 14-PDIP | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CD74HCT107E | Tube | 1,061 | 1 | 
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CD74HCT107E | 26 | 
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CD74HCT107E | 425 | 4 | 
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CD74HCT107E | 340 | 
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CD74HCT107E | 21,945 | 1 | 
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CD74HCT107E | 1 | 
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Texas Instruments CD74HCT109EIC FF JK TYPE DBL 1-BIT 16-PDIP | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CD74HCT109E | Tube | 830 | 1 | 
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CD74HCT109E | 483 | 
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CD74HCT109E | 1,000 | 6 Weeks | 1,000 | 
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CD74HCT109E | 1,060 | 
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CD74HCT109E | 27,587 | 1 | 
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Texas Instruments CD74HCT10EIC GATE NAND 3CH 3-INP 14DIP | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CD74HCT10E | Tube | 420 | 1 | 
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CD74HCT10E | 857 | 
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CD74HCT10E | 8,475 | 808 | 
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CD74HCT10E | 1,000 | 6 Weeks | 1,000 | 
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CD74HCT10E | 75 | 
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CD74HCT10E | 29 | 
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CD74HCT10E | 32,575 | 1 | 
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CD74HCT10E | 814 | 3 | 
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Texas Instruments CD74HCT10MTIC GATE NAND 3CH 3-INP 14SOIC | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CD74HCT10MT | Cut Tape | 238 | 1 | 
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CD74HCT10MT | 5,101 | 1 | 
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CD74HCT10 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
HC10
Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10 
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 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HC10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 | |
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 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140C Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2003  | 
 Original  | 
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140C HC109 HCT109 CD74H CT109) | |
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 Contextual Info: CD74HC107, CD74HCT107 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immu nity and Increased Input Rise and Fall Times  | 
 OCR Scan  | 
CD74HC107, CD74HCT107 CD74HC107 CD74HCT107 HC/HCT73 | |
HC107
Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10 
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 Original  | 
HC107 HCT10 CD74HC107, CD74HCT107 SCHS139 CD74HC107 CD74HCT107 HC107 74HCT 74LS CD74HC107E CD74HCT107E HCT10 | |
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 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10  | 
 Original  | 
CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HCT10 | |
HCT10
Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 
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 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 | |
CD54HC107
Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10 
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 Original  | 
HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10 | |
CD54HC10
Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10 
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 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 | |
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 Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 HC/HCT73 | |
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 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109) | |
| 
 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 | |
"J-K Flip flop"
Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10 
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 Original  | 
HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 "J-K Flip flop" CD54HC107F3A T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M HCT10 | |
HC107
Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10 
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 Original  | 
HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139C HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10 | |
CD54HC10
Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10 
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 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128B HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 | |
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C109
Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 
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 Original  | 
CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 | |
C109
Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 
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 Original  | 
CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 | |
C109
Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 
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 Original  | 
CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140D HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 | |
D74HC10Contextual Info: CD74HC10,0 h a r r is S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-lnput NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC10, CD74HCT10, logic gates utilize silicon gate CMOS technology to achieve operating speeds  | 
 OCR Scan  | 
CD74HC10, CD74HCT10, 74HCT 1-800-4-HARRIS D74HC10 | |
CD74HC10E
Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10 
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 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD74HC10E CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 | |
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 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 | |
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 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109) | |
| 
 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003  | 
 Original  | 
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109) | |
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 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10  | 
 Original  | 
HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 | |
74LS family
Abstract: HCT73 
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 OCR Scan  | 
CD74HC107, CD74HCT107 CD74HC107 CD74HCT107 HC/HCT73 74HCT 74LS family HCT73 | |