CAS31 Search Results

SN74LVC16245

Contextual Info: SN74LVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS S CAS314 -N O V E M B E R 1 9 9 3 - REVISED MARCH 1994 * Member of the Texas Instruments Widebus Family 1 D IR [ 1 1B1 C 2 1B 2 [ 3 GNDÎ 4 • Typical V q h v Output V q h Undershoot > 2 V at Vcc = 3.3 V, TA = 25°C

SN74LVC863

Contextual Info: SN74LVC863 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS S CAS310 - MARCH 1993 - REVISED MARCH 1994 • EPIC Enhanced-Performance implanted CMOS Submicron Process • Typical Vqlp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C * Typical Vqhv (Output Vqh Undershoot)

SN74LVC16373

Contextual Info: SN74LVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS S CAS315 -N O V E M B E R 1 9 9 3 -R E V IS E D MARCH 1994 Member of the Texas Instruments Widebus Family Distributed Vcc and GND pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes

ca3103

Abstract: CAS31-03 CA31 CA2S
Contextual Info: Verarbeitungsmittel für Systeme Minimodul/Multimodul Processing equipment for systems Minimodul/Multimodul Équipement de confectionnement pour systèmes Minimodul/Multimodul CA31-01 CA31-03 CA2 (CA2) CAS31-01 CAS31-03 (CA2S) (CA2S) Halbautomatische Verarbeitungsmaschine für das Anschlagen von Minimodul-/Multimodul-Crimpkontakten

Intel Microprocessor 240440

Abstract: 82360SL intel 82360SL
Contextual Info: in te i November 1992 Intel486 SL Microprocessor SuperSet Data Book Order Number: 241325-001 2-1 Intel486™ SL Microprocessor SuperSet CONTENTS CONTENTS page page 1.0 INTRODUCTION . 2-6 3.0 82360SL I/O SPECIFICATIONS . . . . 2-79

Contextual Info: 47E D SIEMENS • fi23SbOS 0031bl0 <3 ■ SIEG SIEMENS AKTIENGESEL LSCHAF SAB 82C212 Page/Interleave Memory Controller of Siemens PC-AT Chipset Advance Information 157 3.90 M7E » I fl2 3 5 b 0 5 G 0 3 1 b ll SIEMENS AKTIENGESELLSCHAF □ ■ S IE G SAB 82C212

yg 2822

Abstract: RAS 0510 cs8221 neat Waukesha 6670 82C631 82c211 2021G 82C206 CHIPset for 80286 REG62
Contextual Info: PRELIM INARY C S 8221 NEW ENHANCED AT NEAT DATA BOOK 8 2 C 2 1 1 / 8 2 C 2 1 2 / 8 2 C 2 1 5 / 8 2 C 2 0 6 (IPC ) CHIPSet™ 100% IBM™ PC/AT Compatible New En­ hanced CHIPSet™ for 12MHz to 16MHz systems Supports 16MHz 80286 operation with only 0.5-0.7 wait states for 100ns DRAMs and 12

82C211

Abstract: 82c206 ipc P82C211 CS8221 82C206 E4000-H AT-286 S2-221-B CHIPset for 80286 82C215
Contextual Info: CHIP S & T E C H N O L O G I E S INC Tû CHÏPS DE I SOTflllti ODDlOfiD fl T - 5Z-3 3 -0 5 PRELIMINARY CS8221 NEW ENHANCED AT NEAT DATA BOOK 82C211/8 2 C 2 1 2 /8 2 C 2 1 5 /8 2 C 2 0 6 (IPC) CHIPSet™ • 100% IBM7“ PC/AT Compatible New .En­ hanced CHIPSet™ tor 12MHz to 16MHz

sram card 60-pin

Abstract: 33-10L RC-M02J-SF 612J/2H
Contextual Info: Memory Cards Various high quality memory cards from ROHM ROHM offers many series of memory cards so that you can select specific memory card that best matches your system requirements. They have excellent environmental resistance, meaning that the cards can be used under severe temperature,

cd2397

Abstract: RC-M03J-HN PCMCIA SRAM Memory Card 512k 38-pin memory cards
Contextual Info: Memory Cards Various high quality memory cards from ROHM products ROHM offers many series of memory cards so that you can select specific memory card that best matches your system requirements, including size <full, 2 / 3 and half sizes> They have excellent environmental resistance, meaning that the

X-band Gan Hemt

Abstract: x-Band Hemt Amplifier class e power amplifier AM MODULATOR mechanism X-band AM modulation theory polar modulator TEC2005-07985-C03-01 Cree Microwave
Contextual Info: ISMOT 2007 - Dec. 17-21, Monte Porzio Catone Roma - Italy Characterizing the Vdd-to-AM and Vdd-to-PM Nonlinearities in a GaN HEMT Class E Power Amplifier J. A. García*, B. Bedia*, R. Merlín*, P. Cabral*, J. C. Pedro* * Department of Communications Engineering

82C206

Abstract: chipset 82c206 CHIPset for 80286 ARCHITECTURE OF 80286 bios chip manufacturer 80286 chipset 82c206 ipc 80286 82c206 cs8221 neat iAPX 286
Contextual Info: CHIPS P R E L IM IN A R Y ^ f jr 7 ^£ CS8221 NEW ENHANCED AT NEAT DATA BOOK 8 2 C 2 1 1 /8 2 C 2 1 2 /8 2 C 2 1 5 / 8 2 C 2 0 6 (IPC) CHIPSet7 • cf c7 'f5 ~ 'rx 100% IBM™ PC/AT Compatible New En­ hanced CHIPSet™ for 12MHz to 16MHz systems Software Configurable Command Delays,

transistor RCA 467

Abstract: ota ca 3080 RCA 3080 rca CA3080 RCA 467 rca cmos book rca cmos handbook IEEE J. Solid State Circuits, SC "rca application note" rca 1967
Contextual Info: R. L. Geiger and E. Sánchez-Sinencio, "Active Filter Design Using Operational Transconductance Amplifiers: A Tutorial," IEEE Circuits and Devices Magazine, Vol. 1, pp.20-32, March 1985. Active Filter Design Using Operational Transconductance Amplifiers: A Tutorial

Nippon capacitors

Contextual Info: HB56UW272EJN Series, HB56UW264EJN Series 2.097.152-word x 72-bit High Density Dynamic RAM Module 2.097.152-word x 64-bit High Density Dynamic RAM Module HITACHI ADE-203-717B Z Rev.2.0 Jun. 9, 1997 Description The HB56UW272EJN, HB56UW 264EJN belong to 8 Byte DIMM (Dual In-line Memory Module) family,

82C811

Abstract: 82C812 neatsx 82C631 chipset 82c206 386sx chipset 82c211 HA12013 ADTL 84 LIM EMS 4.0
Contextual Info: •■ ■« \ . n « ai it a ■■ H H Preliminary i r 3 TM CS 8281 NEATsx U 12/89 A T A M I M D D A v STK#1 0 0 3 3 -0 0 2 R ev 2 . 0 A I / u r v CS8281 Data Book \ - n Preliminary i r s COPYRIGHT NOTICE Copyright o 1989, Chips and Technologies, Inc. ALL RiGHTS RESERVED,

Contextual Info: HUALQN MICROELECTRONICS im t =i S4E D 4ST6D41 0000040 T HM82C212 MEMORY INTERLEAVED/PAGE CONTROLLER ‘ Features • Page mode access including single bank, 2 way and 4 way p age Interleaved providing higher performance over conventional DRAM addressing schemes.

Contextual Info: HB56UW472EJN Series, HB56UW464EJN Series HB56UW472EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword X 72-bit, 4 k Refresh, 1-Bank Module 18 pcs of 4 M X 4 Components HB56UW464EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword X 64-bit, 4 k Refresh, 1-Bank Module (16 pcs of 4 M X 4 Components)

SN74LVC16374

Contextual Info: SN74LVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCA S316 - N O VEM BER 1993 - REVISED M ARCH 1994 Member of the Texas Instruments Widebus Family EPIC ™ Enhanced-Performance Implanted CMOS Submicron Process Typical V q l p (Output Ground Bounce)

487SX

Abstract: OPTi-486WB v 1.1 82c681 opti 486 chipset
Contextual Info: i 199? OPTi-386/486WB EISA Chipset 82C681/82C682/82C686/82C687 EBC/MCC/1SP/DBC DATABOOK Preliminary Version 1.3 t OPTÏ-386/486WB EISA DATABOOK Version 1.3 PRELIMINARY Disclaimer This specification is subject to change without notice. OPTi, Incorporated assumes no

Diagram of a laptop

Abstract: 82C455 hp laptop battery pinout pinout cartridge HP 82C765 82C601 82C631 82c636 sd832 386sx chipset
Contextual Info: CS8283 LeAPset-sx CHIPSet™ DATA BOOK Revision 1.0 Stock No. 10283-001 Documentation No. CPI68 March 1990 1 CS8283 LeAPset-sx™ CHIPSet™ DATA BOOK Revision 1.0 Stock No. 10283-001 Documentation No. CPI68 COPYRIGHT NOTICE Copyright c 1990, Chips and Technologies, Inc. ALL RIGHTS RESERVED.

Contextual Info: SIEM EN S SAB 82C212 Page/Interleave Memory Controller of Siemens PC-AT Chipset Advance Information 157 3.90 SAB 82C212 • Higher perform ance of DRAM accesses using page m ode access together with a interleaved mem ory accessing scheme • Supports up to 8 MByte on-board

acer adapter circuit diagram

Abstract: cs8221 neat CHIPS TECHNOLOGIES CHIPset for 80286 neat chipset 80286 chipset 82C206 interfacing of memory devices with 80286 rtl 8111 82C212
Contextual Info: CHIPS & TEC HN OL OG IE S INC Tû DE I SOTflllti ODDlOfiD fl T -5 Z -3 3 -0 5 CHIPS PRELIM INARY CS8221 NEW ENHANCED AT NEAT DATA BOOK 8 2 C 2 1 1 /8 2 C 2 1 2 /8 2 C 2 1 5 /8 2 C 2 0 6 (IPC) CHIPSet” Software Configurable Command Delays, Wait states and Memory Organization

C8000H

Abstract: 82c206 ipc 82C212-16 chipset 82c206 82c211 CHIPset for 80286 neat chipset
Contextual Info: SAB 82C212 Page/Interleave Memory Controller of Siemens PC-AT Chipset Siemens PC-AT Chipset Address Busses : Data Busses 4-382 March 1990 Siemens Components, Inc. SAB 82C212 • Higher performance of DRAM accesses using page mode access together with a interleaved memory

LIM EMS 4.0

Abstract: refresh logic ose 29 820212
Contextual Info: HUALQN M I C R O E L E C T R O N I C S iMi=i 54E » • M 5'i6 0 Ml DDDOQMO T HM82C212 MEMORY INTERLEAVED/PAGE CONTROLLER ‘ Features • Page mode access including single bank, 2 way and 4 way p a g e interleaved providing higher performance over conventional DRAM addressing schemes.