CAPACITORS VTT SERIES Search Results

Contextual Info: 19-2335; Rev 0; 1/02 Tracking, Sinking and Sourcing, Synchronous Buck Controller for DDR Memory and Termination Supplies Features ♦ 25A Sourcing and Sinking Current ♦ Automatically Sets VTT to 1/2VDDR ♦ VTT and VTTR Within 1% of 1/2VDDR ♦ Smallest Output Capacitors

fet 2n7002K

Abstract: transistor 123 DL 2n7002k 2k
Contextual Info: 19-2335; Rev 0; 1/02 Tracking, Sinking and Sourcing, Synchronous Buck Controller for DDR Memory and Termination Supplies Features ♦ 25A Sourcing and Sinking Current ♦ Automatically Sets VTT to 1/2VDDR ♦ VTT and VTTR Within 1% of 1/2VDDR ♦ Smallest Output Capacitors

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational

power filter 25v

Abstract: G2996 G2996F1UF G2996F1U G2996P1U SSTL-18
Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational

Contextual Info: LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

Contextual Info: Obsolete Device LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B March 28, 2011 LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational

Contextual Info: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational

G2995

Abstract: G2995F1U G2995P1U
Contextual Info: G2995 Global Mixed-mode Technology Inc. DDR Termination Regulator Features General Description „ The G2995 is a linear regulator designed to meet the JEDEC SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This

UR5595L

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

UR5595

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR  DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. The device

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

Contextual Info: UNISONICTECHNOLOGIESCO., LTD UR5595 CMOS IC DDR T ERM I N AT I ON REGU LAT OR ̈ DESCRI PT I ON The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

UR5595L

Abstract: UR5595L-SH2-R UR5595 UR5595-S08-R UR5595-SH2-R
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.

Contextual Info: Power Capacitors Series/Type: B25834 The following products presented in this data sheet are being withdrawn. Ordering Code B25834L7685K009 B25834L7475K009 B25834L6685K009 Substitute Product Date of Withdrawal 2014-08-14 2014-08-14 2014-08-14 Deadline Last

Contextual Info: Power Capacitors Series/Type: B25835 The following products presented in this data sheet are being withdrawn. Ordering Code B25835M7474K007 B25835M7224K007 B25835M7104K007 Substitute Product Date of Withdrawal 2014-08-14 2014-08-14 2014-08-14 Deadline Last

northbridge

Abstract: UR5596 UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be

ur5596l

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be

Contextual Info: DDR12 Series | Tracking Dual Output DC/DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25A@2.5V for Vddq supply and 8A@1.25V for Vtt termination Tracking dual output voltages 1.25V @ 8A, 2.5V @ 25A

Contextual Info: DDR12 Series | Tracking Dual Output DC-DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25 A @ 2.5 V for Vddq supply and 8 A @ 1.25 V for Vtt termination Tracking dual output voltages 1.25 V @ 8 A, 2.5 V @ 25 A

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR  DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be

4610H-805-201

Abstract: ZO 103 bourns capacitor network
Contextual Info: The 800 Series is obsolete, and not recommended for new designs. PL IA NT Features CO M • Optimizes data transmission in ECL *R oH S systems through proper termination between drivers and receivers ■ Minimizes overshoot, undershoot, and ringing while increasing noise immunity