CAN BUS MEGAFUNCTION Search Results

82c250

Abstract: 82c250 phillips bosch sm drive bosch can 2.0B CAN protocol basics 82C250 CAN engine control module bosch intel 82527 BOSCH Microelectronics 82527 application note
Contextual Info: CAN Bus Megafunction Solution Brief 22 Target Applications: Bus & Interfaces Processor & Peripherals Family: FLEX 10K & FLEX 8000 Vendor: September 1997, ver. 1 Features • ■ ■ ■ ■ ■ ■ Compatible with Controller Area Network CAN Specification 2.0A and 2.0B

BOSCH CAN vhdl

Abstract: PCA82C250T EP1K50-1 EP20K60E-1 BOSCH CAN CONTROLLER vhdl
Contextual Info: Implementation of the Basic CAN specification CAN Bus Controller Megafunction No generated Overload Frames Receiving and transmitting of both identifiers CAN specification 2.0B Programmable data rate up to 1 mbps Programmable baud rate prescaler (up to 1/30)

i2s philips

Abstract: block diagram for asynchronous FIFO testbench of a transmitter in verilog verilog i2s philips I2S bus specification synchronous fifo design in verilog verilog i2s bus Philips Compact Disc Designer Guide
Contextual Info:  Meets Philips Inter-IC Sound Bus Specification  Supported modes I2S-APB Inter-IC Sound Bus Megafunction for AMBA APB − I2S Philips − Left Justified − Right Justified − DSP  Two clock domains − APB the host side clock do- main − system clock for the I2S

EPF6016

Abstract: EPF10K20 EPF10K30 EPF10K50V A-SB-037-01 64-BIT
Contextual Info: 64-Bit PCI Bus Target Megafunction Solution Brief 37 Target Applications: Bus Interfaces Bus Migration Digital Signal Processing DSP High-Speed Communications Family: FLEX 10K & FLEX 6000 Vendor: PLD Applications 14 Rue Soleillet 75971 Paris Cedex 20 France

BYTEBLASTER

Abstract: EPF10K10 EPF10K20 EPF10K30 EPF10K40 2SB26
Contextual Info: PCI Bus Master/Target Interface Megafunction Solution Brief 26 Target Application: Buses & Interfaces Family: FLEX 10K Vendor: PLD Applications 14 Rue Soleillet 75971 Paris Cedex 20 France Tel. 33 01-40-33-79-98 Fax. (33) 01-43-58-14-15 plda@worldnet.fr

verilog code for dma controller

Abstract: DVD read writer BLOCK diagram flash controller verilog code dvd writer block diagram crc verilog code 16 bit ATA-33 EP2C20 EP2S15 sample verilog code for memory read dma controller VERILOG
Contextual Info: Complies with ATA-7 Standard Supports one or two IDE devices ATAIF ATA-7/IDE Host Controller Megafunction Implements a host controller for non-volatile memory devices using the parallel interface known as ATA Advanced Technology Attachment , IDE (Integrated Drive Electronics),

EPM7256

Abstract: BYTEBLASTER EPF10K10 EPF10K50 EPM7256S BITBLASTER Signal Path Designer
Contextual Info: PCI Bus Target Interface Megafunction Solution Brief 25 Target Application: Buses & Interfaces Family: FLEX 10K & FLEX 8000 Vendor: PLD Applications 14 rue Soleillet Paris 75020 France Tel. 33 01-40-33-79-98 Fax. (33) 01-43-58-14-15 plda@worldnet.fr http://www.plda.com

"network interface cards"

Contextual Info: Network interface features o Supports 10/100Mb/s data transfer rates MAC Ethernet Media Access Controller Megafunction o Media Independent Interface MII o Optional Reduced Media In- dependent Interface (RMII) Data link layer functionality o Meets the IEEE 802.3

MAC-1G

Abstract: EP2S15-3 TLSM
Contextual Info: Network interface features o Supports data transfer rates of 10/100/1000 Mbps MAC-1G 1-Gigabit Ethernet Media Access Controller Megafunction o MII/GMII Media Independent Interface o Optional RMII, SMII o PHY management interface* Data link layer functionality

LIN VHDL source code

Abstract: LIN Verilog source code vhdl synchronous parallel bus LIN source code verilog code for frame synchronization vhdl code 8 bit processor buffer register vhdl parallel interface vhdl
Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Megafunction Configurable for support of master or slave functionality 8-bit host controller interface The LIN megafunction is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol

rgb TO HDMI convert chip

Abstract: AD9889B CH7301C lcd qvga 320x240 Sitronix ST7787 ADV7120 RGB24 EP3C40-6 YCbCr TO TFT converter graphic lcd module 320x240
Contextual Info: Generates color and control data for standard displays in the following resolutions: DISPLAY-CTRL High-Resolution Display Controller Megafunction Implements a controller that accepts video data and works with a digital/analog converter DAC to drive standard QVGA (320x240) to WUXGA (1920x1200) displays.

HSCX 82525

Abstract: R8051XC-HDLC hdlc R8051XC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

emmc memory

Abstract: SDXC EMMC HOST CONTROLLER emmc controller emmc eMMC 4.4 ram slot diagram usb sdxc Digital TV receivers block diagram EMMC software
Contextual Info:  Compliant with latest specs − SD Memory Card 3.00 SD, SDHC, and SDXC cards SDIO-HOST SD/SDIO/MMC/e-MMC Card Host Controller Megafunction − SDIO Card 2.00 − MMC and Embedded MMC (e- MMC) Card 4.4 − SD Host 2.00 part A2  Broad compatibility

LIN VHDL source code

Abstract: LIN Verilog source code vhdl synchronous parallel bus LIN protocol verilog code 8 bit buffer register vhdl vhdl code for 8 bit register verilog code for frame synchronization
Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Megafunction Configurable for support of master or slave functionality 8-bit host controller interface The LIN megafunction is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol

verilog code for baud rate generator

Abstract: r8051xc2-b 80517 80C51 R8051XC2 intel 8051 microcontroller INSTRUCTION SET
Contextual Info:  Fully compatible with the MCS 51 instruction set  Single clock per cycle and effi- R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Megafunction cient architecture for up to 12.1 times the performance of original 8051  Fewer machine cycles means

HDTV transmitter receivers block diagram

Abstract: 20 channel GRAPHIC EQUALIZER eureka pci 64 10 channel GRAPHIC EQUALIZER block diagram graphic equalizer image processing DSP asic sican dsp adsl typical "bit error rate" MPEG-4 decoder receiver ADSL Modem circuit diagram
Contextual Info: ¨ Megafunctions Selector Guide System-on-a-Programmable-Chip Solutions June 1999 Contents 2 Introduction to Altera Megafunctions 4 Digital Signal Processing Megafunctions 7 Communications Megafunctions 8 PCI & Other Bus Interface Megafunctions 10 Processor & Peripheral Megafunctions

c programs for fir filter design with 16-bit

Abstract: C32025 TMS320C25
Contextual Info: Control Unit o 16-bit instruction decoding o Repeat instructions for effi- C32025 Digital Signal Processor Megafunction cient use of program space and enhanced execution Central Arithmetic-Logic Unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations

EP1AGX50-6

Abstract: charge controller block diagram
Contextual Info: Compliant with PCI Local Bus Specification, Revision 2.3 66 MHz performance PCI clock frequency PCI-M64 64-bit datapath 64-bit/66MHz PCI Master/Target Interface Megafunction The PCI-M64 megafunction provides a fast, fully-featured, master/target interface that

ep3C5

Abstract: R8051XC
Contextual Info:  Support for Full and Low Speed operation according to the USB 2.0 specification  Generic system bus interface USBFS-DEV  Serial Interface Engine USB Full-Speed Device Controller Megafunction Support full speed devices Extraction clock and data signals

16450S

Abstract: H16450S EP3C40-6
Contextual Info: Capable of running all existing 16450 software H16450S UART with Synchronous CPU Interface Megafunction The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data

Contextual Info: ALTREMOTE_UPDATE Megafunction 2013.08.16 UG-031005 Subscribe Feedback You can configure the features and behavior of the Remote System Upgrade ALTREMOTE_UPDATE megafunction through the MegaWizard Plug-In Manager GUI in the Quartus II software. Related Information

16550S

Abstract: EP3C40-6 EP1K30-1 H16550S
Contextual Info: Capable of running all existing 16450 and 16550a software H16550S UART with FIFOs and Synchronous CPU Interface Megafunction The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data

afdx

Abstract: R8051XC macl
Contextual Info: Network interface features o Supports 10/100Mb/s data transfer rates MAC-L 10/100 Ethernet Media Access Controller Lite Megafunction o Media Independent Interface MII o Optional Reduced Media In- dependent Interface (RMII) o Optional Serial MII interface

EP1C12F324C8

Abstract: EP20K100E-2 PCI-M32 sample vhdl code for memory write
Contextual Info: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Megafunction The main PCI-M32 Interface megafunction purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development.