CADENCE XA 125 2 Search Results

Contextual Info: 3 7 b f i 522 DD 2 0 1 1 E S 47 H P L S B a i GEC P L E S S E Y FEBRUARY 1994 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS2464 - 4.9 MV6639 POCSAG DECODER Supersedes November 1992 edition - DS2464 - 3.3 The MV6639 POCSAG decoder is capable of operating

Contextual Info: FINAL BEYO N D PERFO RM A N CE COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 M A C H 1 11 - 5 /7 /1 0 /1 2 /1 5 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 Pins in PLCC and TQFP

MACH131

Abstract: VANTIS PRO
Contextual Info: FINAL COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 M A C H 1 31 -5 /7 /1 0 /1 2 /1 5 BEYO N D PERFORM ANCE High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 84 Pins in PLCC 64 Macrocells

Contextual Info: FINAL BEYOND PER FO R M A N C E COM ’L: -6/7/10/12/15 IND: -10/12/14/18 M A C H 2 1 1 S P -6 /7 /1 0 /1 2 /1 5 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ JTAG-Compatible, 5-V in-system programming

COOLRUNNER-II examples

Abstract: XA CoolRunner-II XAPP393 VQG44 CoolRunner-II CPLD AEC-Q100 TS16949 XA2C128 XA2C256 XA2C32A
Contextual Info: CoolRunner-II CPLD XA Product Family R DS315-1 v1.0 October 18, 2004 Advance Product Specification Features • • • • • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade. Optimized for 1.8V systems

Contextual Info: FINAL V A N A IM A M D T I COM’L: -15 IND: -20 S C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 144 Pins in PQFP 96 Macrocells 15 ns tPD Commercial, 20 ns tPD Industrial 47.6 MHz fcm102 Inputs with pull-up resistors

Contextual Info: GEC PLESSEY w . S e p te m b e r 1994 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS3984 - 2.8 MV6640 POCSAG DECODER The MV6640 POCSAG decoder is capable of operating at 512 or 1200 baud. This device together with a suitable receiver, provides the major components for a POCSAG pager.

MACH5-128/68-7/10/12/15

Contextual Info: COM’L: -7/10/12/15 PRELIMINARY AMD£I IND: -10/12/15/20 The MACH5-128 MACH5-128/68-7/10/12/15/20 MACH5-128/104-7/10/12/15/20 MACH5-128/120-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

Contextual Info: MÄV i o 1993 IND: -30 Advanced Micro Devices PALLV16V8Z-30 Low-Voltage, Zero-Power 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible — Vcc = +3.0 V to +3.6 V ■ Zero-power CMOS technology

MACH5 from amd

Contextual Info: COM’L: -7/10/12/15 PRELIMINARY AMD£I IND: -10/12/15/20 The MACH5-192 MACH5-192/68-7/10/12/15/20 MACH5-192/104-7/10/12/15/20 MACH5-192/120-7/10/12/15/20 MACH5-192/1 60-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

Contextual Info: FINAL COM’L: -7/10/12/15 IND: -10/12/14/18 VANTI S B E Y O N D P E R FO R M A N C E M A C H 2 2 1 -7 /1 0 /1 2 /1 5 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 68 Pins in PLCC 96 Macrocells

TA138

Abstract: DLM8 TPC-ALS-249 TPC1020B 4584P TA273 CNT4A
Contextual Info: TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS S R FS 001F - D3864, DECEM BER 19B9 - R EVISED FEBRUARY 1993 • • Four Arrays With up to 2000 Usable Equivalent Gates Tl Action Logic System TI-ALS Software for: - ViewLogic™ - Mentor™ - OrCAD/SDT III ™

Contextual Info: , CMX673 ü Microcircuits » Limited U Call Progress Tone Detector M -l-X-E-D S-l-G-N-A-L S-O-L-U-T-i-O-N-S Advance Information D/673/2 May 1998 Features Applications • Worldwide Tone Compatibility • Worldwide Payphone Systems • Single and Dual Tones Detected

APEX nios development board

Abstract: EP1C12 EP1S25F672C8 EP1S30F780C8 EP1S40F780C8 EP20K1000C EP20K200C PRBS altera verilog tcl script ModelSim altera double data rate megafunction sdc
Contextual Info: Quartus II Software Release Notes October 2003 Quartus II version 3.0 Service Pack 2 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your quartus

GWS mini STD

Abstract: Vantis PRO PROGRAMMING SW MACH466-12 vantis jtag schematic
Contextual Info: PRELIMINARY COM’L: -10/12/15 IND:-12/14/18 MACH466/MACHLV466-10/12/15 High-Density EE CMOS Programmable Logic V A N T I S T h e Program m able Logic Co m pany From AM D DISTINCTIVE CHARACTERISTICS • 208 pins in PQFP 100 MHz fQNT ■ Low power 146 Inputs

Contextual Info: FINAL BEYOND PERFORM ANCE COM’L: -10/12/15 IND: -12/14/18 M A C H 2 3 1 S P -1 0 /1 2 /1 5 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ JTAG-Compatible, 5-V in-system programming

Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-512/MACH5LV-512 AMD£I M A C H 5 -5 1 2 /1 2 0 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 6 0 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 8 4 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 9 2 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /

Vantis PRO PROGRAMMING SW

Abstract: VANTIS PRO
Contextual Info: FINAL BEYOND PERFORMANCE COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 M A C H 1 3 1 S P -5 /7 /1 0 /1 2 /1 5 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ JTAG-compatible, 5-V in-system programming

XC6VLX760-FF1760

Abstract: XC6VLX760FF1760-1 XC6VLX760-FF1760-1 XC4VLX15-FF668-10 XC6SLX150T-FGG484-2 FIFO36 FIFO Generator User Guide xilinx logicore fifo generator 6.2 asynchronous fifo vhdl synchronous fifo
Contextual Info: FIFO Generator v5.2 DS317 June 24, 2009 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO

89024

Contextual Info: in te * 89024 2400 BPS INTELLIGENT MODEM CHIP SET For Public Switched Telephone Network and Unconditioned Leased Line Applications • Dial and Re-dial Capability V.22 bis, V.22 A/B, V.21, Bell 212A, and Bell 103 Compatible ■ Full Set of Control Signals for DAA

AT 2005B at

Abstract: AT 2005A 2005b AT 2005B HC240 EP1C12 EP2C20 EP2C50 HC210 HC220
Contextual Info: Quartus II Software Release Notes March 2006 Quartus II version 5.1 Service Pack 2 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your

Contextual Info: FINAL COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ Programmable power-down mode 64 Outputs 64 Flip-flops; 4 clock choices

ad9503

Abstract: N89C026XE 89C024 290181
Contextual Info: in t e i 89C024XE HIGH PERFORMANCE 2400 BPS INTELLIGENT MODEM CHIP SET Simple Serial Interface to External NVRAM Support for Error Correction MNP* Class 4/5 Easily Customized Command Set and Features CHMOS For Public Switched Telephone Network and Unconditioned Leased

MACH466/MACHLV466-10/12/15

Contextual Info: PRELIMINARY COM’L :-10/12/15 AMD£I MACH466/MACHLV466-10/12/15 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 208 pins in PQFP ■ 100 MHz fCNT ■ Low power ■ 146 Inputs ■ 5-V and supply operation versions available ■ 128 Outputs