BW16 Search Results

rac 16a 400v

Abstract: BW250EAG BW250JAGU
Contextual Info: Molded Case Circuit Breakers List of products G-TWIN Standard Series IEC/EN/GB/JIS conformed Line protection Motor protection AC415V BW32 BW50 BW63 BW100 BW125 BW160 BW250 BW400 BW630 BW800 AC415V BW32 BW50 BW63 BW100 BW125 BW250 Icu Icu 1.5kA AAG AAG 2.5kA

BW1610J2F

Abstract: BW1610 English Electric Valve eev triode tube 7586 MA323 MA85E eev tube industrial tube company Triode 805
Contextual Info: BW1610J2F R.F. POWER TRIODE The data should be read in conjunction with the Power Triode Preamble. ABRIDGED DATA The BW1610J2F is a water cooled power triode of coaxial ceramic/metal con­ struction, intended primarily for industrial service. It has an integral water

CY8C38

Abstract: CY8C3866 Cypress touch panel BOSCH CONNECTOR CATALOG CY8C3866LTI-068 CY8C3866PVI-070 CY8C3866AXI-039
Contextual Info: PSoC 3: CY8C38 Family Datasheet ® Programmable System-on-Chip PSoC General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal

TAG 8926

Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Contextual Info: MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual MCIMX31RM Rev. 1 2/2006 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

Contextual Info:  CY7C1143KV18/CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

Contextual Info: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth

Contextual Info: CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.0 cycles:

Contextual Info: CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36)

Contextual Info: CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

CY7C1382DV33-200BZI

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)

Contextual Info: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:

Contextual Info: CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 72-Mbit Density 2 M x 36 CY7C1521KV18 – 2 M × 36 ■ 250 MHz Clock for High Bandwidth Functional Description ■

Contextual Info: 5V, 100mA Low Dropout Linear Regulator with WATCHDOG, RESET, & WAKE UP D escrip tion The CS-8151 is a precision 5V, 100mA micro-power voltage regulator with very low quiescent current 400pA typical at 200}iA load . The 5V output is accurate within ±2% and supplies

Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18

CY7C1354C

Abstract: CY7C1356C
Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz

8XC196KC Users manual

Abstract: 8XC196KC/KD complete users manual 8XC196KC/KD MCS-96 mcs 96 programming 8XC196KC/kd users manual MCS-96 development 8XC196KD users manual 8XC196KB Users manual 8XC196KC instructions
Contextual Info: AP-714 APPLICATION NOTE Converting from the 8XC196KB KC KD to the 8XC196Nx Family JENNIE ABELLA APPLICATIONS ENGINEER July 1995 Order Number 272625-001 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in

Contextual Info: CY7C1518KV18, CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36

Contextual Info: Data sheet BMA222E Data sheet Page 1 BMA222E Digital, triaxial acceleration sensor Bosch Sensortec BMA222E: Data sheet Document revision 1.0 Document release date 21 May 2013 Document number BST-BMA222E-DS004-03 Technical reference code s 0 273 141 168 Notes

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■