BUS TRANSCEIVERS Search Results

DM74ALS

Abstract: DM74ALS645A DM74ALS645AN DM74ALS645AWM DM74ALS645
Contextual Info: DM74ALS645A Octal Bus Transceivers General Description These octal bus transceivers are designed for asynchronous two-way communication between data busses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction

pin diagram priority decoder 74138

Abstract: 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D uPB8289 8284 clock intel 8289 8289 bus arbiter
Contextual Info: SEC mPB8289 BUS ARBITER NEC Electronics Inc. D escription Pin C onfiguration The /j P B8289 bus arbiter is used with the/iPB8288 bus controNer to interface 8086 and 8088 microprocessors to a multi master system bus. The fiPB8289 controls the ¿iPB8288 bus controller and the bus transceivers

74*645

Contextual Info: ♦Octal Bus Transceivers non-inverted 3-state outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data • PIN ARRANGEMENT from the A bus to the B bus or from the B bus to the A bus de­

1S2074

Abstract: 74LSOO HD74LS645 Hitachi Scans-001
Contextual Info: ♦Octal Bus Transceivers non-inverted 3-state outputs • PIN ARRANGEMENT This octal bus transceiver is designed for asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­

Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed for asynchronous two-way IPIN ARRANGEMENT communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­

DM74LS645

Abstract: DM74LS645N DM74LS645WM MS-001 MS-013
Contextual Info: Revised March 2000 DM74LS645 Octal Bus Transceiver General Description Features These octal bus transceivers are designed for asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the

74LSOO

Abstract: HD74LS641
Contextual Info: • O c t a l Bus Transceivers non-inverted open-collector outputs This octal bus transceivers is designed for asynchronous two-way IPIN ARRANGEMENT communication between data buses. The devices transmit data, from the A bus to the B bus or from the B bus to the A bus de­

1S2074

Abstract: 74LSOO HD74LS640 AL667
Contextual Info: • Octal Bus Transceivers inverted 3-state outputs Th is octal bus transceivers is designed for asynchronous two-way com m unication between data buses. Th e device transmit data from the A bus to the 6 bus or from the B bus to the A bus depending upon the level at the direction control (D IR ) input.

B0283

Contextual Info: Am26S10/Am26Sl1 Quad Bus Transceivers DISTINCTIVE CHARACTERISTICS • • • • Input to bus is inverting on Am26S10 Input to bus is non-inverting on Am26S11 Quad high-speed open collector bus transceivers Driver outputs can sink 100mA at 0.8V maximum Bus compatible with Am2905, Am2906, Am2907

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

5A5B

Contextual Info: HD 74LS640. O ctal Bus Transceivers inverted 3-s ta te outputs This octal bus transceivers is designed fo r asynchronous tw o -w ay co m m unicatio n betw een data buses. IPIN ARRANGEMENT T h e device transm it data fro m th e A bus to th e 8 bus or fro m th e B bus t o th e A bus

UT54ACS164245SEI

Contextual Info: UT54ACS164245SEI RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet June 19, 2007 www.aeroflex.com/16BitLogic LOGIC SYMBOL FEATURES • Flexible voltage operation - 5V bus to 3.3V bus; 5V bus to 5V bus - 3.3V bus to 5V bus; 3.3V bus to 3.3V bus

N8T26AN

Abstract: N8T28N
Contextual Info: 8T26A, 28 Signefics Bus Transceivers 3-State Quad Bus Transceiver Product Specification Logic Products FEATURES • 200 mA bus loading • Ideal for: - Half-duplex data transmission - Memory interface buffers - Data routing in bus oriented systems - High current drivers

Contextual Info: IDT74LVCH16652A 3.3 V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD device is organized as two independent 8-bit bus transceivers with 3-state D-type registers. The control circuitry is organized for multiplexed transmission of data between A bus and B bus

1983-R

Contextual Info: SN74ALS638A, SN74ALS639A, SN74AS638A, SN74AS639 OCTAL BUS TRANSCEIVERS SDAS123A - DECEMBER 1983 - REVISED JANUARY 1995 Bidirectional Bus Transceivers in High-Density 20-Pin Packages Choice of True or Inverting Logic A-Bus Outputs Are Open Collector; B-Bus Outputs Are 3 State

LS645

Abstract: 74ls642 SN54/74LS642 SN54LSXXXJ LS640 LS641 LS642 74LS645 8A79 74LS641
Contextual Info: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic

Contextual Info: SN54/74LS640 SN54/74LS641 SN54/74LS642 SN54/74LS645 OCTAL BUS TRANSCEIVERS These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic

AM26S10

Contextual Info: Am26S10/Am26S11 Am26SlO/Am26S11 Quad Bus Transceivers DISTINCTIVE CHARACTERISTICS Input to bus is inverting on Am26S10 Input to bus is non-inverting on Am26S11 Quad high-speed open collector bus transceivers Driver outputs can sink 100mA at 0.8V maximum •

Contextual Info: I L C DATA DEVICE CORP b5E ]> UJISIISS ILC DATA DEVICE HbTÔTb'ï QDQÔBS'i D4b « D D C BUS-6310011 SERIES CORPORATION _ MIL-STD-1553 DATA BUS SINGLE AND DUAL TRANSCEIVERS A PPR O X. VS ACT U A L S IZ E FEATURES BUS-63102 II • BUS-63125 II BUS-63105 II

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

SN74LS245

Abstract: SN74LS245N 80021 SN54LS245 SN54LS245J SN74LS245DBR SN74LS245DW SN74LS245DWR SN74LS245NSR SNJ54LS245J
Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

SN54LS245

Abstract: SN54LS245J SN74LS245 SN74LS245DBR SN74LS245DW SN74LS245DWR SN74LS245N SN74LS245NSR SNJ54LS245J 80021012A
Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

SN74LS245N PRICE

Abstract: 80021012A 8002101SA
Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

80021012A

Abstract: 8002101SA
Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins