BUS DRIVERS Search Results

Contextual Info: DS26S10 DS26S10 Quad Bus Transceiver Literature Number: SNOSBL4 DS26S10 Quad Bus Transceiver General Description The DS26S10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers.

piezo injector

Abstract: Automotive ECU IC automotive ecu circuit engine diesel injector MOSFET driver WSLT2512
Contextual Info: Diesel ECU and Fuel Injector Drivers Table of Contents CAN-BUS, ESD Protection. 3 CAN-BUS, ISO9141 Bus Transceiver. 4

N8T26AN

Abstract: N8T28N
Contextual Info: 8T26A, 28 Signefics Bus Transceivers 3-State Quad Bus Transceiver Product Specification Logic Products FEATURES • 200 mA bus loading • Ideal for: - Half-duplex data transmission - Memory interface buffers - Data routing in bus oriented systems - High current drivers

IDT74ALVCH16823

Abstract: SO56-2
Contextual Info: IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH16823 registers, I/O ports, bidirectional bus drivers with parity, and working

NS859

Abstract: DS26S10 DS26S10N DS26S11 N16A
Contextual Info: DS26S10 Quad Bus Transceiver General Description The DS26S10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to the high speed

Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

AC13

Abstract: AF14
Contextual Info: ispLSI 5512V In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Generic

t16 400

Abstract: 5384VA AF14
Contextual Info: ispLSI 5384V In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

C1996

Abstract: DS26S10 DS26S10C DS26S10CJ DS26S10M DS26S11 DS26S11C DS26S11M 5802 DS26S10CN
Contextual Info: DS26S10C DS26S10M DS26S11C DS26S11M Quad Bus Transceivers General Description The DS26S10 and DS26S11 are quad Bus Transceivers consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0 8V and 4 high speed bus receivers Each driver output is connected internally to

IC SN74HC

Abstract: EB209 USE OF TRANSISTOR SN74HC SN74HC00 SN74HC541 SN74HCT541 3 bus system
Contextual Info: EB209E Bus-Hold Function EB209E BUS HOLD CIRCUIT Author: Eilhard Haseloff Translated by Tristam Pye Rev.: A Date: 02-19-1995 1 Applikationslabor EB209E Bus-Hold Function When developing systems using CMOS circuits, the engineer must pay particular attention to the operating conditions in which all drivers of a bus are

1N918

Abstract: DS26S11 DS26S10 DS26S10CJ DS26S10CN DS26S10MJ J16A
Contextual Info: DS26S10C/DS26S10M/DS26S11C/DS26S11M Quad Bus Transceivers General Description The DS26S10 and DS26S11 are quad Bus Transceivers consisting of 4 high speed bus drivers w ith open-collector outputs capable o f sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to

N24C

Abstract: DM74AS646NT DM74AS646WM DM74AS648NT DM74AS648WM M24B DM74ALS648NT DM74AS646
Contextual Info: DM74AS646/DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs

pin diagram priority decoder 74138

Abstract: 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D uPB8289 8284 clock intel 8289 8289 bus arbiter
Contextual Info: SEC mPB8289 BUS ARBITER NEC Electronics Inc. D escription Pin C onfiguration The /j P B8289 bus arbiter is used with the/iPB8288 bus controNer to interface 8086 and 8088 microprocessors to a multi master system bus. The fiPB8289 controls the ¿iPB8288 bus controller and the bus transceivers

Bus-Interface Packaging and Processing

Abstract: MPC555 MOTOROLA 934
Contextual Info: SECTION 9 EXTERNAL BUS INTERFACE The MPC555 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC555 architecture supports

DS26S11

Abstract: DS26S11C DS26S10 DS26S10C DS26S10CN
Contextual Info: General Description The DS26S10 and DS26S11 are quad Bus Transceivers consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to the high speed bus receiver in addition to being connected to

MOTOROLA 934

Abstract: MPC566 MPC565
Contextual Info: SECTION 9 EXTERNAL BUS INTERFACE The MPC565 / MPC566 external bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC565 /

MOTOROLA 944

Abstract: MPC561 MPC563
Contextual Info: SECTION 9 EXTERNAL BUS INTERFACE The MPC561 / MPC563 external bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC561 /

MPC555

Abstract: MOTOROLA 935
Contextual Info: SECTION 9 EXTERNAL BUS INTERFACE The MPC555 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC555 architecture supports

MIL-STD-1553

Abstract: common mode rejection ratio test 1553B HLP-6000 MIL-STD-1553A QPL-21032-31
Contextual Info: MIL-STD-1553 DATA BUS PRODUCTS continued from previous page • TRANSFORMERS TYPE PACKAGE DESCRIPTION/FEATURES BUS-25679 BUS-27765 BUS-29854 BUS-41429 Bus Isolation Transformers 0 .6 3 x 0 -6 3 x 0 .3 " Module Provides all of the turns ratio configurations, component isolation, and common

vqfp package pinout

Abstract: PCMCIA Z16017 z53c8003fsc 100-Pin Package Pin-Out Diagram scsi evaluation board
Contextual Info: Mass Storage Bus Interface Zilog Superintegration Pr oducts Guide PCMCIA Bus Z16017 Block Diagram Address Decoder Window Decoder Five Configuration Registers Peripheral PCMCIA Bus Bus Peripheral Bus I/F 16-Bit Address Decoder Window Decoder Five Configuration

0011B

Abstract: 0040H 80960MC M82965
Contextual Info: Advanced Processor Bus 7 CHAPTER 7 ADVANCED PROCESSOR BUS Efficient bus utilization is essential in a multiprocessing system. A simple and efficient approach to building an 80960MC processor interconnect system is to use the Advanced Processor bus AP-bus

DM74ALS240A

Abstract: 74ALS DM74ALS1240A DM74ALS1240AWM DM74ALS241A MS-013
Contextual Info: Revised February 2000 DM74ALS1240A Octal 3-STATE Bus Driver General Description Features These octal 3-STATE bus drivers are designed to provide the designer with flexibility in implementing a bus interface with memory, microprocessor, or communication systems,

Contextual Info: IDT74ALVCH16276 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD INDUSTRIAL TEMPERATURE RANGE IDT74ALVCH16276 3.3V CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER WITH BUS-HOLD DESCRIPTION: FEATURES: This 12-bit synchronous bus exchanger is built using dual metal CMOS

74ALS646-1NT

Abstract: 74ALS646-1WM DM74ALS646NT DM74ALS646WM M24B N24C DM74ALS646
Contextual Info: DM74ALS646/74ALS646-1 Octal 3-STATE Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.