BUS DRIVERS Search Results

Contextual Info: DS26S10 DS26S10 Quad Bus Transceiver Literature Number: SNOSBL4 DS26S10 Quad Bus Transceiver General Description The DS26S10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers.

piezo injector

Abstract: Automotive ECU IC automotive ecu circuit engine diesel injector MOSFET driver WSLT2512
Contextual Info: Diesel ECU and Fuel Injector Drivers Table of Contents CAN-BUS, ESD Protection. 3 CAN-BUS, ISO9141 Bus Transceiver. 4

N8T26AN

Abstract: N8T28N
Contextual Info: 8T26A, 28 Signefics Bus Transceivers 3-State Quad Bus Transceiver Product Specification Logic Products FEATURES • 200 mA bus loading • Ideal for: - Half-duplex data transmission - Memory interface buffers - Data routing in bus oriented systems - High current drivers

IDT74ALVCH16823

Abstract: SO56-2
Contextual Info: IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH16823 registers, I/O ports, bidirectional bus drivers with parity, and working

ISPLI

Abstract: 5000VA TQFP 144 PACKAGE lattice
Contextual Info: ispLSI 5512VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Generic

5000VA

Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

NS859

Abstract: DS26S10 DS26S10N DS26S11 N16A
Contextual Info: DS26S10 Quad Bus Transceiver General Description The DS26S10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to the high speed

C1996

Abstract: DS7834 DS7834J DS8834 DS8834N J16A N16A
Contextual Info: DS7834 DS8834 Quad TRI-STATE Bus Transceivers General Description Features This family of TRI-STATE bus transceivers offers extreme versatility in bus organized data transmission systems The data bus may be unterminated or terminated DC or AC at one or both ends Drivers in the third high impedance state

Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

Contextual Info: ispLSI 5512VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Generic

5000VA

Abstract: 5256VA 5384VA 5512VA
Contextual Info: ispLSI 5512VA In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Generic

5000VA

Abstract: 5384VE-100LF256 5384VE BGA 256 PACKAGE power dissipation GLB11 TPD16
Contextual Info: ispLSI 5384VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

AC13

Abstract: AF14
Contextual Info: ispLSI 5512V In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Generic

5000VA

Abstract: 5256VA 5384VA 5512VA 67-Ball bga BGA98
Contextual Info: ispLSI 5384VA In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Global Routing Pool GRP

5000VA

Contextual Info: ispLSI 5512VE In-System Programmable 3.3V SuperWIDE High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Generic

C1996

Abstract: DS26S10 DS26S10C DS26S10CJ DS26S10M DS26S11 DS26S11C DS26S11M 5802 DS26S10CN
Contextual Info: DS26S10C DS26S10M DS26S11C DS26S11M Quad Bus Transceivers General Description The DS26S10 and DS26S11 are quad Bus Transceivers consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0 8V and 4 high speed bus receivers Each driver output is connected internally to

Contextual Info: Semiconduc DS26S10 ^ j^ N a tio n a l or DS26S10 Quad Bus Transceiver General Description The D S 26S 10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers.

IC SN74HC

Abstract: EB209 USE OF TRANSISTOR SN74HC SN74HC00 SN74HC541 SN74HCT541 3 bus system
Contextual Info: EB209E Bus-Hold Function EB209E BUS HOLD CIRCUIT Author: Eilhard Haseloff Translated by Tristam Pye Rev.: A Date: 02-19-1995 1 Applikationslabor EB209E Bus-Hold Function When developing systems using CMOS circuits, the engineer must pay particular attention to the operating conditions in which all drivers of a bus are

1N918

Abstract: DS26S11 DS26S10 DS26S10CJ DS26S10CN DS26S10MJ J16A
Contextual Info: DS26S10C/DS26S10M/DS26S11C/DS26S11M Quad Bus Transceivers General Description The DS26S10 and DS26S11 are quad Bus Transceivers consisting of 4 high speed bus drivers w ith open-collector outputs capable o f sinking 100 mA at 0.8V and 4 high speed bus receivers. Each driver output is connected internally to

N24C

Abstract: DM74AS646NT DM74AS646WM DM74AS648NT DM74AS648WM M24B DM74ALS648NT DM74AS646
Contextual Info: DM74AS646/DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs

pin diagram priority decoder 74138

Abstract: 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D uPB8289 8284 clock intel 8289 8289 bus arbiter
Contextual Info: SEC mPB8289 BUS ARBITER NEC Electronics Inc. D escription Pin C onfiguration The /j P B8289 bus arbiter is used with the/iPB8288 bus controNer to interface 8086 and 8088 microprocessors to a multi master system bus. The fiPB8289 controls the ¿iPB8288 bus controller and the bus transceivers

Bus-Interface Packaging and Processing

Abstract: MPC555 MOTOROLA 934
Contextual Info: SECTION 9 EXTERNAL BUS INTERFACE The MPC555 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC555 architecture supports

Bus Switches

Abstract: AN-5021 FSTU32160
Contextual Info: Fairchild Semiconductor Application Note October 2000 Revised October 2006 Bus Switch Undershoot Protection: Which Systems Need this Protection and Why Bus switches have become commonplace in may system applications. Bus switches are used for bus isolation, bus

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Bus Driver/Receiver w ith 4 -to -1 Output M ultiplexers The MC10H332 is a Dual Bus Driver/Receiver with multiplexers. These multiplexers have common selects When disabled, OE = high the bus outputs go to -2 .0 specified are with 25 Q loading on the bus drivers and