BUS DOOR Search Results

"printer controller"

Abstract: 486 system bus 6502 CPU door bell AB-2061G-33 MO-112 RH15
Contextual Info: AB-2061G-33 33Mhz PCI to Local Bus Interface for 8 or 16 bit Local Bus Applications 32- to 16- bit PCI to local bus translator AB-2061-33 33Mhz PCI to Local Bus Interface Product Specification AB Semicon AB-2061-33 32 bit to 8 or 16 bit PCI to local bus translator

9060ES

Abstract: PCI9060ES PCI9060SD small endian AD-1508
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132

NM93CS46

Abstract: PCI9060ES PCI9060SD 10B5 9060ES 93CS56
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132

PCF85063A

Abstract: PCA9541A
Contextual Info: I2C-bus Components Selection Guide I2C-bus Components Selection Guide Overview TABLE OF CONTENTS Overview . . . . . . . . . . . . . . . . 1 I2C-bus System Diagram . . . . 2 General Purpose Input Output GPIO Expanders . . . 3 Thermal Sensors and Voltage Management . . . . . . 6

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

amcc part marking

Abstract: AMCC S5335 S5335QFAAB AMCC DATE CODE MARKING "serial nvram" S5335 K10101A nv ram data sheet pic 92121 s5935
Contextual Info: Part Number S5335 Revision 5.01 – November 30, 2005 S5335 Data Sheet PCI Bus Controller, 3.3V S5335 PCI BUS CONTROLLER MATCH MAKER AMCC Confidential and Proprietary DS1657 Revision 5.01 – November 30, 2005 S5335 – PCI Bus Controller, 3.3V Data Sheet

V363EPC

Abstract: V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC
Contextual Info: V363EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed/Demultiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface

PIN CONFIGURATION pci 32 bit 5 v

Abstract: 9060ES 9060SD RC32364 RC5000 pci 32 bit 5 v
Contextual Info: Support Components PLX Technology Inc. PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features Description ◆ PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ◆ Programmable local bus supports nonmultiplexed 32-bit

9060ES

Abstract: 9060SD MPC860 9985K
Contextual Info: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and

9060ES

Abstract: A236
Contextual Info: Use of A236 Parallel Video DSP Chip with a PCI Bus Application Note: Use of A236 Parallel Video DSP Chip with a PCI Bus Revised February 3, 1999 1. Summary This Application Note explains how to connect an A236 Chip to a single PCI bus. The PCI originally named the Peripheral Component Interconnect bus is widely used in many computer

9060ES

Abstract: 9060SD MPC860
Contextual Info: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and

doorbell application

Abstract: doorbell circuit application doorbell PCI I/O 9060ES 9060SD Intel i960 intel i960 series PCI9060
Contextual Info: PCI PLX TECHNOLOGY PCI 9060 • ■ ■ ■ ■ ■ ■ PCI Bus Master Interface Supporting i960 Microprocessor Based Adapters and Systems Two Independent DMA Channels For Local Bus Memory to PCI Host Bus Data Transfers Four Bidirectional FIFOs For Zero

MPC860

Contextual Info: PCI 9054 PCI Bus Master I/O Accelerator Chip Highlights • PCI v2.2 compliant 32-bit 33MHz Bus Master Interface Controller enables PCI Burst Transfers up to 132Mbytes/second ■ General Purpose Bus Master Interface featuring an advanced Data Pipe Architecture which

Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation

Contextual Info: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

PCI 9656 schematic

Abstract: MPC860 RC32364
Contextual Info: VERSION 1.0 2002 PCI 9056 Connectivity 32-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC and Generic 32-bit, 66MHz Local Bus Designs • 32-bit, 66MHz PCI r2.2 compliant ■ Motorola PowerQUICC and generic 32-bit, 66MHz local bus

S5933QE

Abstract: Intel 8237 dma controller block diagram AMI eeprom bios amcc s5933 S593X ami bios EMB4 24C04 24C08 256X8
Contextual Info: A MCC ARCHITECTURAL OVERVIEW S5933 INTRODUCTION TO THE PCI LOCAL BUS FEATURES The local bus concept was developed to break the PC data bottleneck. Traditional PC bus architectures are inadequate to m eet the demands of today's graphics-oriented system s and large application

PC107A

Abstract: microprocessor PC107
Contextual Info: PC107A PCI Bridge Memory Controller Datasheet Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1

Contextual Info: Make sure the next Card you purchase has. BU-66318 ACE-BRIDGE FEATURES • PCI to Local Bus Bridge • Local Bus Compatible with ACE, Mini-ACE, Enhanced Mini-ACE, MicroACE and Mini-ACE Mark3 Series Generations • PCI Bus Interface Connects up to Six

GT-64260

Abstract: GT64260 DDC 1553
Contextual Info: Make sure the next Card you purchase has. BU-66318 ACE-BRIDGE FEATURES • PCI to Local Bus Bridge • Local Bus Compatible with ACE, Mini-ACE, Enhanced Mini-ACE, MicroACE and Mini-ACE Mark3 Series Generations • PCI Bus Interface Connects up to Six

PAR64

Abstract: REQ64
Contextual Info: PCI Bus Applications on FPGAs Introduction The Peripheral Component Interconnect PCI bus is a highĆbandwidth, plugĆandĆplay" bus designed to meet the performance demands of the peripherĆ als of today's highĆperformance PCs and workstaĆ tions and their large bandwidth applications. It is

80C2000

Abstract: "Embedded Programmable Interrupt Controller" circuit diagram of doorBELL Tsi107
Contextual Info: Tsi107 Host Bridge for PowerPC Processor Interface • Supports the Motorola MPC603e, MPC7xx, and MPC74xx processors • Supports the IBM PowerPC 603e, and PowerPC 7xx processors • Processor bus frequency up to 133 MHz • 64/32-bit data bus, 32-bit address bus

V360EPC-50LPA1

Abstract: v360epc-50lp V360EPC-33LP 29030 V360EPC V360EPC-33LPA1 V380SDC V96BMC V96SSC SPACE BRIDGE SEMICONDUCTOR
Contextual Info: V360EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit De-Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®