BUS DATA Search Results

VII-320

Abstract: MIL-STD-1553A
Contextual Info: QQ0 ILC DATA DEVICE CORPORATION«_ BUS-69008/09/18/19/23/24/25/28/29II REAL-TIME SOFTWARE FOR THE BUS-6551711 IDEA CARD FEATURES DESCRIPTION These real-time software libraries, the BUS-69008II, BUS-69009II, BUS-6901811, BUS-6901911, BUS-69023, BUS-69024,

UT54ACS164245SEI

Contextual Info: UT54ACS164245SEI RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet June 19, 2007 www.aeroflex.com/16BitLogic LOGIC SYMBOL FEATURES • Flexible voltage operation - 5V bus to 3.3V bus; 5V bus to 5V bus - 3.3V bus to 5V bus; 3.3V bus to 3.3V bus

Contextual Info: Interrupt controller 16-bit peripheral data bus Peripheral address bus 16-bit internal Y data bus Internal Y address bus Internal X address bus CPU 16-bit internal X data bus 32-bit internal data bus CDB Buffer Internal address bus (CAB) ROM Block Diagram

MCF5307

Abstract: MCF5206
Contextual Info: MCF5307 EXTERNAL BUS INTERFACE MCF5307 External Bus Motorola ColdFire 1- 1 MCF5307 EXTERNAL BUS INTERFACE ▼ MCF5307 External Bus Interface – ColdFire® synchronous standard bus interface – 32-bit address bus, 32-bit data bus unmultiplexed – 3-clock basic bus cycle

Library

Abstract: BUS-65515
Contextual Info: BBS BUS-69050 SERIES ILC DATA DEVICE CORPORATIONS_ "C" SOFTWARE LIBRARY TO SUPPORT THE BUS-61553, BUS-61559, BUS-65515, BUS-65522II, -full I BUS-65529, BUS-65531, and BUS-65555 d a ta sheet DESCRIPTION fi\/MLABl-E_ Free software is now available to sup­

69051

Contextual Info: 000 BUS-69050 SERIES ILC DATA DEVICE CORPORATION_ "C" SOFTWARE LIBRARY TO SUPPORT THE BUS-61553, BUS-61559, BUS-65515, BUS-65522H, Tuo I BUS-65529, BUS-65531, and BUS-65555 DATASHEETftVA t l a b l e _ Features DESCRIPTION Free softw are is now available to sup­

bus arbitration

Abstract: uPD70216 UPD70208H
Contextual Info: NEC juPD70208H, 70216H 6. BAU BUS ARBITRATION UNIT The BAU perform s bus arbitration am ong bus masters. A list o f bus masters (units w hich can acquire the bus) is shown below. Table 6-1 Bus Masters Bus M aster Bus Cycle CPU Program fetch, data read/write

MPC555

Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC566

Abstract: MPC565
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC555

Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

mpc556

Abstract: MPC555 inl2u
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC555

Abstract: MPC556
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC561

Abstract: MPC563 motorola 1116
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

EP201

Abstract: LFX1200B MPC8260 PowerPC 8260
Contextual Info: Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.

bus arbitration

Abstract: EP201 LFX1200B MPC8260
Contextual Info: Eureka Technology Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.

WG128128B

Abstract: db3 datasheet POWER SUPPLY for LED DSA0017310 42VLED
Contextual Info: WG128128B Graphic type DB0 Data bus line DB1 Data bus line Data bus line DB2 DB3 DB4 Data bus line Data bus line DB5 Data bus line DB6 Data bus line DB7 Data bus line Date / Instruction seiect RS R/W E CS RES VO VDD Date read / write Enable singnal Chip select

29 bit

Abstract: SH7709
Contextual Info: UBC CPG/WDT 16-bit peripheral data bus 1 INTC Peripheral address bus 1 TLB SH3 CPU 32-bit data bus MMU 32-bit virtual address bus MLT RTC TMU CCN BSC SCI CACHE IrDA 16-bit peripheral data bus 2 DMAC Peripheral address bus 2 32-bit data bus 2 29-bit physical address bus 2

transistor smd marking 2a1

Abstract: Bidirectional Multipurpose Registered Transceiver UT54ACS164646S 1B6 SMD
Contextual Info: Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet July 2010 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION ‰ Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus

521A1

Contextual Info: Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet March 2009 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION ‰ Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus

UT54ACS164646S

Contextual Info: Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet May 17, 2012 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION  Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus

Contextual Info: Standard Products UT54ACS164646S RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet January 2008 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION ‰ Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus

DM54ALS640AJ

Abstract: DM74ALS DM74ALS640AN DM74ALS640AWM J20A
Contextual Info: DM54ALS640A/DM74ALS640A Inverting Octal Bus Transceivers General Description Features These inverting octal bus transceivers are designed for asynchronous two-way communication between data bus­ ses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level

BUS-65518

Contextual Info: EJ00 ILC DATA D EV ICE C O R P O R A T IO N !_ BUS-69008/18/23/24/25/28/29/35II REAL-TIME SOFTWARE FOR THE BUS-6551711 IDEA CARD AND BUS-65518 CARD FEATURES DESCRIPTION These real-time software libraries, sup­ ported by the BUS-69008II, BUS-69009II, BUS-6901811, BUS-6901911, BUS-69023,

SH7615

Abstract: bus ethernet Hitachi DSA0084
Contextual Info: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller DSP Hitachi user debug interface X-RAM Serial I/O Serial communication interface