BUS CONTROLLER Search Results

Contextual Info: Interrupt controller 16-bit peripheral data bus Peripheral address bus 16-bit internal Y data bus Internal Y address bus Internal X address bus CPU 16-bit internal X data bus 32-bit internal data bus CDB Buffer Internal address bus (CAB) ROM Block Diagram

SH7615

Abstract: bus ethernet Hitachi DSA0084
Contextual Info: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller DSP Hitachi user debug interface X-RAM Serial I/O Serial communication interface

SH7706

Contextual Info: Block Diagram MMU L bus I bus 1 TLB CPU UBC CCN AUD SCI Peripheral bus 1 1.2 TMU CACHE RTC BRIDGE BSC SCIF DMAC CPG/WDT CMT Peripheral bus 2 INTC I bus 2 H-UDI ADC DAC External bus interface Legend ADC : A/D converter AUD : Advanced user debugger BSC : Bus state controller

"Ethernet Controller"

Abstract: Hitachi DSA0084 SH7616 controller
Contextual Info: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller Serial I/O with FIFO DSP Hitachi user debug interface X-RAM Serial I/O Serial communication

pin diagram priority decoder 74138

Abstract: 8284 clock generator intel 8284 clock generator MULTIMASTER 74149 PB8289D uPB8289 8284 clock intel 8289 8289 bus arbiter
Contextual Info: SEC mPB8289 BUS ARBITER NEC Electronics Inc. D escription Pin C onfiguration The /j P B8289 bus arbiter is used with the/iPB8288 bus controNer to interface 8086 and 8088 microprocessors to a multi master system bus. The fiPB8289 controls the ¿iPB8288 bus controller and the bus transceivers

Contextual Info: Chapter 5 Bus Operations The TurboSPARC microprocessor contains four bus controllers along with four dedicated bus interfaces. 1. Secondary cache bus interface and controller 2. Main memory DRAM bus interface and controller 3. SBus interface and controller

1553 bus controller

Abstract: BUS-65515 DDC 1553 BUS-65600
Contextual Info: D D C BUS-65600 ILC DATA DEVICE CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES • BUS-65600 is available as MIL-DWG DESC 5962-88585-01XC. DESCRIPTION The BUS-65600 is a dual redundant MIL-STD-1553 Bus Controller (BC), Re­

Contextual Info: ^ 001 4, x y BUS-65610 _ ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged

0xF008

Abstract: all ic data high level block diagram for i2c controller S5N8946
Contextual Info: I2C BUS CONTROLLER S5N8946 ADSL/CABLE MODEM MCU 6 I2C BUS CONTROLLER OVERVIEW The S5N8946′s internal IC bus (I2C-bus) controller has the following important features: — It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I2C-bus is free,

Z80 i2c INTERFACING

Abstract: intel 8049 8051 using I2C BUS PCA9564 intel 8051 architecture PCA9564 Intel 8051 20 MHz PCA9564BS-T motorola 6800 datasheet z80 intel 8051 microcontroller architecture
Contextual Info: NXP I2C-bus and Bus controller PCA9564 Easy interfacing between serial I2C-bus and 8-bit parallel communication bus This simple-to-use bus controller makes it easy to create a bidirectional interface between the serial I2C-bus and the 8-bit parallel bus system used by most standard microcontrollers and

4038X

Abstract: BUS-27765 BUS-65201 590i4 A5690 BUS-65101 BUS-66106 BUS-66111
Contextual Info: 0 0 BUS-661068a n d BUS-66111 ILC DATA DEVICE CORPORATION MIL-STD-1553 BUS CONTROLLER PROTOCOL HYBRIDS BUS-66106 FEATURES • GENERATES PROTOCOL, TIMING AND CONTROL FOR MIL-STD-1553 OR MACAIR A5690 BUS CONTROLLER • SUPPORTS ALL MESSAGE FORMATS DESCRIPTION

BUS-65201

Contextual Info: QOQ BUS-66106*a n d BUS-66111 ILC DATA DEVICE CORPORATION MIL-STD-1553 BUS CONTROLLER PROTOCOL HYBRIDS BUS-66106 FEATURES • GENERATES PROTOCOL, TIMING AND CONTROL FOR MIL-STD-1553 OR MACAIR A5690 BUS CONTROLLER • SUPPORTS ALL MESSAGE FORMATS DESCRIPTION

F8H SMD

Abstract: DIP20 HVQFN20 JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665 SO20
Contextual Info: PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 03 — 12 August 2008 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

DIP20

Abstract: HVQFN20 JESD22-A114 JESD22-A115 JESD78 PCA9564 PCA9665 SO20
Contextual Info: PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 02 — 7 December 2006 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

F8H SMD

Contextual Info: PCA9665; PCA9665A Fm+ parallel bus to I2C-bus controller Rev. 4 — 29 September 2011 Product data sheet 1. General description The PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

bck-01

Abstract: RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 BUS-65600 A09 N03 BUS-65610
Contextual Info: □01 4, > 7 BUS-65610 _ ILC DATA DEVICI CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR APPROX. Vs ACTUAL SIZE FEATURES • DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit

PIN DIAGRAM OF 80286

Abstract: kc 4369 SAB 80287 82C206 CHIPset for 80286 80287 80286 data bus MD sab82c206 82c206 ipc 80286 chipset
Contextual Info: SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset 4-342 March 1990 Siemens Components, Inc. SAB 82C211 • SAB 80286 bus interface and bus control • CPU/AT bus state machine and bus arbitration logic • Clock generator with software speed selection logic optional independent AT

MPC561

Abstract: MPC563 IMB3
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC566

Abstract: MPC565 NOTES ON MULTIPLEXER
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC555

Abstract: 7f90
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

Motorola MPC555

Abstract: MPC555 MPC556
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC556

Abstract: MPC555 7fa0
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC555

Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

SAB82C206

Contextual Info: SIEMENS SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset Advance Information 117 3.90 SAB 82C211 • SAB 80286 bus interface and bus control • • • CPU/AT bus state machine and bus arbitration logic • Clock generator with software speed selection logic optional independent AT