BUS ARBITER Search Results

MACH465

Abstract: 85C30 MACH465-12 EZ-030 AM29030 D1667 29030 27C010 MACH220 MAX232
Contextual Info: Using a PC I Bus as the I /O Bus on an Am29030/040 M icroprocessor Design Application Note This application note describes how the Peripheral Component Interconnect (PCI) bus can be used as the I/O bus portion on a two-bus microcontroller design. Additionally, one

NM93CS46

Abstract: PCI9060ES PCI9060SD 10B5 9060ES 93CS56
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132

bus arbitration

Abstract: p22v10 VME bus arbitration AN900 GAL22V10 gal22v10 application
Contextual Info: VME Bus Arbitration Using a GAL 22V10 Figure 1. The Bus Arbitration Process Introduction The GAL22V10 provides a quick solution to bus arbitration and control needs. In this application note, we discuss how a VME bus arbitration circuit can be easily implemented within a GAL22V10, while leaving logic

VME bus arbitration

Abstract: p22v10 bus arbitration GAL22V10 bus arbiter
Contextual Info: VME Bus Arbitration Using a GAL 22V10 Figure 1. The Bus Arbitration Process Introduction The GAL22V10 provides a quick solution to bus arbitration and control needs. In this application note, we discuss how a VME bus arbitration circuit can be easily implemented within a GAL22V10, while leaving logic

74S245

Abstract: pin configuration 74LS32 74LS32 pin configuration 74LS764
Contextual Info: SCB68175 Signetics Bus Controller Preliminary Specification Microprocessor Products PIN CONFIGURATION DESCRIPTION FEATURES The Signetics SCB68175/8X821 Bus Controller is a high-speed bus requester and timing generator designed to inter­ face a local m aster typically, a m icro­

Zoran 888

Abstract: UV618 Zoran ZR36120 ZR36110 ZR36120 CS4920 SAA2502 SAA7110 SAA7111 SAA7188
Contextual Info: < lllk ZR36120 Multimedia Controller for PCI Bus Data Sheet Features • Glueless interface to PCI bus. PCI spec. 2.1 compliance . I C bus master port. ■ Glueless interface to MPEG decoders (e.g., ZR36100/ ZR36110), video digitizers (e.g., SAA 7110, SAA 7111),

TDA 11106

Abstract: ami bios 486dx vesa local bus ldev intel 486SL 82c596 am486 Block Diagram AMI bios power management E5EF 486 system bus 486dx isa bios
Contextual Info: PRELIMINARY C Y PR E SS Features • Provides an interface between the PCI Local Bus and the CPU bus • PCI Bus Rev. 2.0 compliant • Supports Intel 486DX, 486DX2, 486SX, 486SL, P24T, AMD AM486 and Cyrix Cx486S2 M6/M7 CPUs • Interfaces with Cypress CY82C596 or

SLLU003

Abstract: SLLA020A 5962-9752901 TSB12LV21AI
Contextual Info: TSB12LV21A PCILynx IEEE 1394-1995 BUS TO PCI BUS INTERFACE SLLS273 – APRIL 1997 D D D D D D Supports Provisions of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus† Performs the Function of a 1394 Cycle Master Supports 1394 Transfer Rates of 100, 200

TSB12LV21

Abstract: TD15
Contextual Info: TSB12LV21 PCILynx IEEE 1394-1995 BUS TO PCI BUS INTERFACE SLLS244 – JULY 1996 D D D D D D Supports Provisions of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus† Performs the Function of a 1394 Cycle Master Supports 1394 Transfer Rates of 100, 200

Contextual Info: C h a pter 3 MB86832 Bus Interface Unit 3.1 Overview of Bus Interface Unit The BIU on the MB86832 offers the following features: • Option to run core at multiplied frequency of the Bus Interface Unit, x l, x2, x3, x4. • Four-word burst mode for instruction fetches and data loads,

flexi packet microwave

Abstract: MICROWIRE eeprom interface am79c960 errata PE-65421 pulse ST7032 10BASE PQB132 PQT144 16S02
Contextual Info: Am79C970A PCnet -PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product DISTINCTIVE CHARACTERISTICS n Single-chip Ethernet controller for the Peripheral Component Interconnect PCI local bus n Supports ISO 8802-3 (IEEE/ANSI 802.3) and

sdram controller

Abstract: Single Data Rate SDRAM Memory Controller EP504 I960 PCI AHB DMA memory bandwidth
Contextual Info: Eureka Technology EP504 AHB Bus to SDRAM Controller Product Summary FEATURES • SDRAM controller interfaces directly with AHB Bus and user interface. • Built-in arbitration between two access ports. • Second access port allows memory sharing with user logic devices.

AMD 79c97* lance

Contextual Info: PRELIMINARY AMDH Am79C971 PCnet -fi4ST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus DISTINCTIVE CHARACTERISTICS • Single-chip Fast Ethernet controller for the Peripheral Component Interconnect PCI local bus — 32-bit glueless PCI host interface

Contextual Info: intel. INTEL 82557 FAST ETHERNET PCI BUS CONTROLLER Optimum Integration for Lowest Cost Solution — IEEE 802.3 10Base-T and 100Base-T compatible — Glueless 32-bit PCI bus master interface — Flash support up to 1 Mbyte High Performance Networking Functions

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

Contextual Info: PRELIMINARY Am79C970 PCnet -PCI Single-Chip Ethernet Controller for PCI Local Bus Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Periph­ eral Component Interconnect PCI local bus ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and

TI2000

Abstract: TI380 TI380PCI TI380C2X
Contextual Info: TI380PCI PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS SPWS020 – AUGUST 1995 D D D D D D D D D Glueless Interface Between the Peripheral Component Interconnect PCI Bus and the TI380C2x Family of Processors Compliant With PCI Specification, Revision 2.0†

Z684

Abstract: MSM13R0000 MSM98R000 pbeb Signal Path Designer Z684-PCI s/z684 bridge
Contextual Info: Z684 PCI Bus Controller 0.5µ m Technology Mega Macrocell DESCRIPTION The PCI Bus Controller Mega Macrocell is a featured element in OKI’s 0.5µm Sea of Gates SOG and Customer Structured Array (CSA) families. Designers can significantly reduce design and simulation effort

9200ns

Abstract: 95288XL 80960JD TMS320C6000 TMS320C6203 TQ144 XC95288XL NS-301 dt 9250 vhdl EMIF
Contextual Info: Application Report SPRA674 - May 2000 TMS320C6000 Expansion Bus: Multiple DSP to i80960Kx/Jx Microprocessor Interface Zoran Nikolic DSP Applications ABSTRACT This application note describes interface between two TMS320C6000 DSPs and the i80960Jx/Kx microprocessor via the TMS320C6000 DSP expansion bus. This application report

KS8723

Abstract: "network interface cards"
Contextual Info: KS8723 – Single Port 10/100 PHY / MAC / PCI 486 Mercury Drive, Sunnyvale, California 94085 VDET SERRN PERRN STOPN DEVSELN TRDYN IRDYN FRAMEN PAR CBEN[3:0] AD[31:0] REQN WAKE INTAN IDSEL PCI Bus Interface TxDMA Logic Tx FIFO Logic TxFIFO RAM Highlights Bus

Contextual Info: PRELIMINARY INTEL 380FB PCISET: 82380AB MOBILE PCI-TO-ISA BRIDGE MISA PCI Bus at 25 MHz to 33 MHz • PC/PCI DMA Protocol for Software Transparent, Low Pin Count DMA on ISA ■ Supports 3 ISA Slots ■ 160-lead MQFP Package ISA Bus at 7.5 MHz to 8.33 MHz

AMD 79c97* lance

Contextual Info: P R E LIM IN A R Y AM DÎI Am79C970A PCnet -PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Periph­ eral Component Interconnect PCI local bus ■ Supports optional Boot PROM for diskless

Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features • Provides control for the cache, system memory, and the PCI bus • PCI Bus Rev. 2.1 compliant • Supports 3V Pentium™, AMD K5, K6, and Cyrix 6x86 M1 CPUs • Support for WB or WT L1 cache

Contextual Info: in te i 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz